Vertical channel memory devices with nonuniform gate electrodes and methods of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsDaehong Eom, Kyunghyun Kim, Kwangsu Kim, Jun-Youl Yang, Se-Ho Cha
Life of this patent
Estimating the term…
Abstract
A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
Claims15
A method comprising:
- forming a mold stack comprising alternating insulation layers and sacrificial layers on a substrate;
- forming vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack;
- removing portions of the sacrificial layers in a first part of the mold stack to form first spaces and to leave portions of the sacrificial layers remaining between the insulation layers in a second part of the mold stack;
- enlarging the first spaces by removing portions of the insulating layers and/or the vertical channel regions;
- removing the remaining portions of the sacrificial layers in the second part of the mold stack to form second spaces between the insulating layers after enlarging the first spaces;
- and
- forming gate electrodes in the first and second spaces.
A method comprising:
- forming a mold stack comprising alternating insulation layers and sacrificial layers on a substrate;
- forming vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack;
- and
- forming gate electrodes between adjacent ones of the insulation layers and surrounding the vertical channel regions wherein the gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.
The method of claim 18, further comprising forming at least one data storage layer on the vertical channel regions before forming the gate electrodes and wherein forming gate electrodes comprises forming the gate electrodes on the at least one data storage layer.
The method of claim 18, wherein the gate electrodes decrease in thickness away from the sidewalls of the insulation layers in a stepwise or gradual manner.
Dependencies are inferred from the claim text.