Semiconductor device and manufacturing method thereof
AssigneeFujitsu Semiconductor Limited
InventorMasashi Shima
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Abstract
A semiconductor device including a low-concentration impurity region formed on the drain side of an n-type MIS transistor, in a non-self-aligned manner with respect to an end portion of the gate electrode. A high-concentration impurity region is placed with a specific offset from the gate electrode and a sidewall insulating film. The semiconductor device enables the drain breakdown voltage to be sufficient and the on-resistance to decrease. A silicide layer is also formed on the surface of the gate electrode, thereby achieving gate resistance reduction and high frequency characteristics improvement.
Claims10
A semiconductor device manufacturing method comprising:
- forming a first impurity region of a first conductivity type in a specific region above a substrate;
- forming a gate electrode above the substrate with a first insulating film therebetween so that the gate electrode overlaps with an end portion of the first impurity region;
- forming a second impurity region of the first conductivity type in the substrate, opposite the first impurity region;
- forming a second insulating film on a sidewall of the gate electrode;
- forming third and fourth impurity regions of the first conductivity type in the substrate, opposite each other and next to the first and second impurity regions, respectively, by masking the first impurity region a specific distance away from the second insulating film, the third and fourth impurity regions having an impurity concentration higher than the first and the second impurity regions;
- and
- forming a silicide layer above each surface of the gate electrode and the third and the fourth impurity regions.
Dependencies are inferred from the claim text.