Super-self-aligned trench-dmos structure and method

A method for manufacturing a vertical semiconductor device comprising:

• a) forming a body layer in an epitaxial layer wherein the epitaxial layer is of a first semiconductor type and the body is of a second semiconductor type;
• b) forming a trench in the epitaxial layer;
• c) lining a bottom and one or more sidewalls of the trench with a gate insulating layer;
• d) forming a gate electrode in the trench in the body and epitaxial layer, wherein the gate oxide is disposed between the gate electrode and the body and between the gate electrode and the epitaxial layer;
• e) forming a cap insulator over the gate electrode;
• f) etching back around the cap insulator such that the top of the gate electrode is even with or protrudes above a surface of the epitaxial layer;
• g) forming a spacer on the epitaxial layer self-aligned to the cap insulator, wherein the spacer includes a heavy concentration of dopants of the first semiconductor type and wherein the spacer is self-aligned to the cap insulating layer, and wherein forming the spacer comprises depositing a layer of material and then anisotropically etching back the layer of material with an etch selective to the insulator cap such that only the spacer is left and the body layer next to the spacer is etched back below the bottom of the spacer;
• h) diffusing at least a portion of the dopants of the spacer into the body layer to form a source region below the spacer wherein the source region is of the first semiconductor type;
• and
• i) implanting a body contact region containing dopants of a second semiconductor type in the body and annealing the body contact region, wherein implanting a body contact region is self-aligned to the spacer;
• and
• j) forming a metal layer over the insulator cap, spacer, source region and body contact region.