US 2014/0004661 A1 · METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Abstract

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Claims21

Dependent claims

1-17. (canceled)

A method of manufacturing a semiconductor device, comprising the steps of:

(a) providing a wiring substrate including a first surface, a bonding lead formed over the first surface, a first solder material formed over the bonding lead, a second surface opposite to the first surface, and a land formed over the second surface,
wherein the bonding lead is extended along a first direction in plan view,
wherein the bonding lead has a first portion, a second portion integrally formed with the first portion, and a third portion integrally formed with the second portion,
wherein the second portion is arranged between the first portion and the third portion,
wherein a width of the second portion is less than a width of each of the first and third portions in the plan view, and
wherein the width of each of the first, second and third portions is along a second direction crossing the first direction;
and
(b) after the step (a), disposing a semiconductor chip over the first surface of the wiring substrate such that a main surface of the semiconductor chip faces the first surface of the wiring substrate, and electrically connecting a bonding pad of the semiconductor chip with the bonding lead of the wiring substrate,
wherein the semiconductor chip includes the main surface, the bonding pad formed over the main surface, a pillar formed over the bonding pad, a second solder material formed over an end face of the pillar, and a back surface opposite to the main surface, and
wherein the semiconductor chip is disposed over the wiring substrate such that the second portion of the bonding lead overlaps with the pillar.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/013,304Filed 29 Aug 2013

Priority

JP 2011-14543130 Jun 2011

Published

2 Jan 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification34 codes

H10W 90/701
Package configurations: characterised by the relative positions of pads or connectors relative to package parts
H10P 72/7402
Using temporarily an auxiliary support: wafer tapes, e.g. grinding or dicing support tapes
H10W 70/099
Package substrates; Interposers; Redistribution layers [RDL]: connecting interconnections to insulating or insulated package substrates,…
H10W 70/65
Characterised by their interconnections: shapes or dispositions of interconnections

Method of manufacturing semiconductor device

Life of this patent

Method of manufacturing semiconductor device

Life of this patent

Abstract

Claims21