Method for producing chip stacks
AssigneeInfineon Technologies AG
InventorsHans-Joachim BARTH, Harald SEIDL
Life of this patent
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Abstract
The present disclosures relates to a method for producing ultrathin chip stacks and chip stacks. Generally, a plurality of first semiconductor chips is formed in a wafer. A second semiconductor chip is applied to each of the plurality of first semiconductor chips via a connection layer and a stabilization layer is applied to fill in the interspace between each of the second semiconductor chips. The wafer, semiconductor chip, and stabilization layer are thinned and the wafer is diced to produce a plurality of singulated chip stacks.
Claims25
A method for producing chip stacks, comprising:
- forming a plurality of unsingulated first semiconductor chips in a wafer, each of the plurality of unsingulated first semiconductor chips comprising a first chip connection area;
- applying a singulated second semiconductor chip via an electrically conductive layer to each of the plurality of unsingulated first semiconductor chips, each of the unsingulated first semiconductor chips and singulated second semiconductor chips being permanently electrically connected;
- filling a continuous interspace region that extends between each of the singulated second semiconductor chips with a stabilization layer up to a predetermined height;
- thinning at least one of the wafer, the stabilization layer, and the singulated second semiconductor chips;
- forming an opening that extends through the stabilization layer to an electrical connection area at a surface of the wafer;
- and
- dicing the wafer to produce a plurality of singulated chip stacks, wherein the interspace region extends to a top surface of the chip stack.
A method for producing chip stacks, comprising:
- forming a plurality of unsingulated first semiconductor chips in a wafer, each of the plurality of unsingulated first semiconductor chips comprising a first chip connection area;
- applying a singulated second semiconductor chip via an electrically conductive layer to each of the plurality of unsingulated first semiconductor chips, each of the unsingulated first semiconductor chips and singulated second semiconductor chips being permanently electrically connected;
- filling a continuous interspace that extends between each of the singulated second semiconductor chips with a stabilization layer up to a predetermined height;
- thinning at least one of the wafer, the stabilization layer, and the singulated second semiconductor chips to a predetermined distance from a stop layer in at least one of the wafer, the stabilization layer, and the singulated second semiconductor chips;
- thinning at least one of the wafer, the stabilization layer, and the singulated second semiconductor chips to the stop layer in at least one of the wafer, the stabilization layer, and the singulated second semiconductor chips, wherein the stop layer substantially automatically stops the thinning;
- and
- dicing the wafer to produce a plurality of singulated chip stacks.
Dependencies are inferred from the claim text.