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US 2013/0314142 A1Published application
Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission
AssigneeFujitsu Limited
InventorsHirotaka TAMURA, Masaya KIBUNE
Life of this patent
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Abstract
A phase-combining circuit for combining cyclic timing waveforms that have been phase-controlled by control signals based on three or more input signals of different phases, has a weight signal generating circuit and a weighting circuit. The weight signal generating circuit generates weights according to the control signals, and the weighting circuit gives the weights to the respective input signals, with a positive or negative polarity for each one signal.
Claims11
A timing signal generator circuit comprising:
- a control code generating circuit for generating a first digital control for phase control;
- a control code converting circuit for converting said first digital control code and thereby generating a second digital control code;
- and
- a weighted sum generating circuit for generating a sum by applying weights to a plurality of phase clock signals input thereto, said weights being generated in accordance with said second digital control code, wherein:
- the relationship between said first digital control code and the phase of an output clock is controlled by adjusting the relationship between said first digital control code and said second digital control code;
- and
- wherein said second digital control code includes a larger number of bits than said first digital control code.
4 more elements
A timing signal generator circuit comprising:
- a control code generating circuit for generating a first digital control code for phase control;
- a control code converting circuit for converting said first digital control code and thereby generating a second digital control code;
- a weighted sum generating circuit for generating a sum by applying weights to a plurality of phase clock signals input thereto, said weights being generated in accordance with said second digital control code;
- and
- a comparator circuit for converting the output of said weighted sum generating circuit into a clock, wherein:
- the relationship between said first digital control code and the phase of an output clock is controlled by adjusting the relationship between said first digital control code and said second digital control code;
- and
- said second digital control code includes a larger number of bits than said first digital control code.
5 more elements
A timing signal generator circuit comprising:
- a control code generating circuit for generating a first digital control code for phase control;
- a control code converting circuit for converting said first digital control code and thereby generating a second digital control code;
- a weighted sum generating circuit for generating a sum by applying weights to a plurality of phase clock signals input thereto, said weights being generated in accordance with said second digital control code;
- and
- a storage circuit for storing said second digital control code corresponding to said first digital control code, wherein:
- the relationship between said first digital control code and the phase of an output clock is controlled by adjusting the relationship between said first digital control code and said second digital control code;
- said second digital control code includes a larger number of bits than said first digital control code;
- and
- a conversion is performed by reading said corresponding second digital control code from said storage circuit in accordance with an up-down signal responsive to said first digital control code.
6 more elements
A timing signal generator circuit comprising:
- a control code generating circuit for generating a first digital control code for phase control;
- a control code converting circuit for converting said first digital control code and thereby generating a second digital control code;
- a weighted sum generating circuit for generating a sum by applying weights to a plurality of phase clock signals input thereto, said weights being generated in accordance with said second digital control code;
- a correction weight generator circuit for correcting the weight assigned to each of said phase clock signals;
- and
- a correction code generating circuit for generating from said first digital code a correction code for controlling the correction weight that said correction weight generator circuit generates, wherein:
- the relationship between said first digital control code and the phase of an output clock is controlled by adjusting the relationship between said first digital control code and said second digital control code;
- said second digital control code includes a larger number of bits than said first digital control code;
- and
- a combination of said first digital control code and said correction code, in effect, constitutes said second digital control code.
7 more elements
Dependencies are inferred from the claim text.