Method of performing circuit simulation and generating circuit layout
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHui Yu LEE, Feng Wei KUO, Jui-Feng KUAN, Simon Yi-Hung CHEN
Life of this patent
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Abstract
A method of generating a circuit layout of an integrated circuit includes generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit. A consolidated netlist including information from the original netlist and the layout geometry parameters is generated. Then, the circuit layout is generated based on the consolidated netlist.
Claims20
A method of generating a circuit layout of an integrated circuit, the method performed by a hardware controller, the method comprising:
- generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit;
- generating a consolidated netlist according to the original netlist and the layout geometry parameters;
- and
- generating the circuit layout based on the consolidated netlist.
A method of performing a circuit simulation for an integrated circuit, the method performed by a hardware controller prior to generation of a circuit layout of the integrated circuit, the method comprising:
- generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit;
- generating a consolidated netlist according to the original netlist and the layout geometry parameters;
- generating a modified netlist based on the consolidated netlist, the modified netlist being recognizable by a simulation software program;
- and
- performing, by executing the simulation software program, the circuit simulation based on the modified netlist.
A non-transitory computer readable storage medium encoded with a computer program code, the computer program code being arranged to cause a hardware controller to:
- generate layout geometry parameters for at least a predetermined portion of an original netlist of an integrated circuit, the layout geometry parameters comprising length of diffusion geometric parameters, well proximity effect geometric parameters, poly space effect geometric parameters, oxide diffusion (OD) space effect geometric parameters, or boundary effect geometric parameters;
- and
- generate a consolidated netlist according to the original netlist and the layout geometry parameters, wherein the generation of the consolidated netlist comprises replacing layout-dependent effect related (LDE-related) instance parameters in the original netlist with the layout geometry parameters to obtain the consolidated netlist.
Dependencies are inferred from the claim text.