Method and Apparatus for Reading NAND Flash Memory

A method for providing a continuous data output from a NAND memory array to a data bus through a page buffer, the page buffer having a data register and a cache register, comprising:

• storing NAND memory array data in the data register;
• transferring a first portion of data from a first portion of the data register to a first portion of the cache register;
• subsequent to the first data portion transferring step, performing a first ECC computation on data in the first cache register portion;
• subsequent to the first ECC computation performing step, outputting data from the first cache register portion to the data bus;
• transferring a second portion of data from a second portion of the data register to a second portion of the cache register;
• subsequent to the second data portion transferring step, performing a second ECC computation on data in the second cache register portion;
• and
• subsequent to the second ECC computation performing step, outputting data from the second cache register portion to the data bus;
• wherein the first cache register portion outputting step and the second cache register portion outputting step are performed continuously and in alternation;
• wherein the first ECC computation performing step is performed during the second cache register portion outputting step;
• and
• wherein the second ECC computation performing step is performed during the first cache register portion outputting step.

A flash memory comprising:

• a NAND flash memory array;
• a row decoder coupled to the NAND flash memory array;
• a data register coupled to the NAND flash memory array;
• a cache register coupled to the data register;
• an ECC circuit coupled to the cache register;
• a column decoder coupled to the cache register;
• a control circuit coupled to the row decoder, the column decoder, the data register, the cache register, and the ECC circuit;
• wherein the cache register is organized in a plurality of portions, and the data register is organized in a plurality of portions respectively corresponding to the cache register portions;
• and
• wherein the control circuit comprises logic and register elements for executing the functions of:
• reading data from the NAND flash memory array to the data register;
• transferring data from the data register portions to the respective cache register portions, in alternation;
• performing error correction with the ECC circuit on data in the cache register portions in alternation, to provide ECC processed data in the cache register portions;
• and
• outputting the ECC processed data from the cache register portions to the control circuit, seamlessly and in alternation;
• wherein execution of the data transferring function and the ECC processed data outputting function for a particular one of the cache register portions is adapted for different times;
• and
• wherein execution of the error correction performing function and the ECC processed data outputting function for a particular one of the cache register portions is adapted for different times.

A NAND flash memory comprising:

• a NAND flash memory array;
• a row decoder coupled to the NAND flash memory array;
• a one page data register coupled to the NAND flash memory array;
• a page of transmission gates;
• a one page cache register coupled to the data register through the transmission gates;
• a column decoder coupled to the cache register;
• and
• a control circuit coupled to the row decoder, the column decoder, the data register, the cache register, and the transmission gates, wherein a first group of the transmission gates, and a second group of the transmission gates distinct from the first group, are separately and independently controllable.