Methods and Devices to Reduce Outer Code Failure Rate Variability

A method of operating a solid state non-volatile memory device having multi-level memory cells configured to store more multiple bits of data, the method comprising:

• encoding data into inner code words, the inner code words arranged according to MSB pages comprising most significant bits (MSBs) of the memory cells and LSB pages comprising least significant bits (LSBs) of the memory cells, the MSB and LSB pages sequentially accessed in a particular order;
• encoding page groups of MSB pages and LSB pages into outer codes, each page group having a substantially equal number of MSB pages and LSB pages;
• and
• storing the encoded page groups in the memory device, wherein encoding the page groups and storing the encoded page groups includes intermittently accumulating the outer code parity for each of the page groups as the pages are sequentially stored in the memory device according to the particular order.

A solid state memory device comprising:

• an inner encoder configured to encode data into inner code words arranged according to pages of the memory device, the pages associated with failure rate information;
• page grouping circuitry configured to group the pages to reduce variability in outer code failure;
• an outer encoder configured to encode the pages of page groups into outer codes, the outer encoder including a parity generator configured to intermittently accumulate the outer code parity for each of the page groups as the pages are sequentially stored in the memory device according to the particular order;
• and
• modulator circuitry configured to store the encoded pages in memory cells of the memory device.