Apparatus for Predicate Calculation in Processor Instruction Set
AssigneeApple Inc.
InventorsRajat Goel, Sandeep Gupta, Yamini Modukuru
Life of this patent
Estimating the term…
Abstract
An apparatus and method for calculating flag bits is disclosed. The flag bits may be used in a processor utilizing branch predication. More particularly, the apparatus and method may be used to calculate a predicate that can be used by a branch unit to evaluate whether a branch is to be taken. In one embodiment, the apparatus is coupled to receive a condition code associated with an instruction, and flag bits generated responsive to execution of the instruction. The condition code is indicative of a condition to be checked resulting from execution of the instruction. The apparatus may then provide an indication of whether the condition is true.
Claims25
An apparatus comprising:
- first and second multiplexers configured to receive, respectively, first and second pluralities of data bits each associated with a condition code of an instruction;
- an execution unit configured to, responsive to execution of the instruction, provide a first set of flag bits as selection bits to the first multiplexer and a second set of flag bits as selection bits to the second multiplexer;
- and
- a first logic circuit configured to output an indication of whether a condition associated with the condition code is true based on outputs received from the first and second multiplexers.
A method comprising:
- providing first and second pluralities of data bits to first and second multiplexers, respectively, wherein the first and second pluralities of data bits are associated with a condition code of an instruction;
- providing a first set of flag bits to select inputs of the first multiplexer responsive to execution of the instruction;
- providing a second set of flag bits to select inputs of the second multiplexer responsive to execution of the instruction;
- generating an indication of whether a condition associated with the condition code is true based on outputs provided by the first and second multiplexers.
A processor comprising:
- a status register configured to provide a condition code associated with an instruction;
- an execution unit configured to generate a plurality of flag bits responsive to execution of the instruction;
- and
- a predicate unit including:
- a plurality of multiplexers each coupled to receive a respective plurality of data bits generated based on the condition code, and wherein each of the plurality of multiplexers is further configured to receive one or more of the flag bits as select inputs;
- and
- an output unit configured to, based on respective outputs from each of the plurality of multiplexers, set an output bit if a condition indicated by the condition code is true.
A method comprising:
- providing a first modified version of a condition code to data inputs of first multiplexer and a second modified version of the condition code to data inputs of a second multiplexer;
- generating a plurality of flag bits responsive to executing, in an execution unit, an instruction associated with the condition code;
- providing a first set of the plurality of flag bits as select inputs to the first multiplexer and a second set of the plurality of flag bits to the second multiplexer;
- determining, based on outputs of the first multiplexer, the second multiplexer, and a logic unit, whether a condition indicated by the condition code is true.
An integrated circuit comprising:
- a first multiplexer having a respective plurality of data inputs coupled to receive a first modified condition code and a respective plurality of select inputs coupled to receive a first set of a plurality of flag bits;
- a second multiplexer having a respective plurality of data inputs coupled to receive a second modified condition code and a respective plurality of select inputs coupled to receive a second set of the plurality of flag bits;
- a logic unit configure to receive selected ones of the plurality of flag bits, including at least one flag bit from the first set and at least one flag bit from the second set;
- and
- an output unit configured to provide an indication whether a particular condition indicated by an unmodified condition code is true based on outputs from the first multiplexer, the second multiplexer, and the logic unit.
Dependencies are inferred from the claim text.