Method and apparatus for batching memory requests
AssigneeAdvanced Micro Devices, Inc.
InventorsGabriel H. Loh, Rachata Ausavarungnirun
Life of this patent
Estimating the term…
Abstract
A memory controller includes a batch unit, a batch scheduler, and a memory command scheduler. The batch unit includes a plurality of source queues for receiving memory requests from a plurality of sources. Each source is associated with a selected one of the source queues. The batch unit is operable to generate batches of memory requests in the source queues. The batch scheduler is operable to select a batch from one of the source queues. The memory command scheduler is operable to receive the selected batch from the batch scheduler and issue the memory requests in the selected batch to a memory interfacing with the memory controller.
Claims24
A memory controller, comprising:
- a batch unit comprising a plurality of source queues for receiving memory requests from a plurality of sources, each source being associated with a selected one of the source queues, wherein the batch unit is operable to generate batches of memory requests in the source queues;
- a batch scheduler operable to select a batch from one of the source queues;
- and
- a memory command scheduler operable to receive the selected batch from the batch scheduler and issue the memory requests in the selected batch to a memory interfacing with the memory controller.
A computer system, comprising:
- a memory;
- a plurality of processing units operable to issue memory requests for accessing the memory;
- and
- a memory controller, comprising:
- a batch unit comprising a plurality of source queues for receiving memory requests from a plurality of sources, each source being associated with a selected one of the source queues, wherein the batch unit is operable to generate batches of memory requests in the source queues;
- a batch scheduler operable to select a batch from one of the source queues;
- and
- a memory command scheduler operable to receive the selected batch from the batch scheduler and issue the memory requests in the selected batch to a memory interfacing with the memory controller.
A method, comprising:
- receiving a plurality of memory requests from a plurality of sources for accessing a memory;
- storing the memory request in one of a plurality of source queues to generate batches of memory requests in the source queues, wherein each source is associated with a selected one of the source queues;
- selecting a particular batch from one of the source queues;
- and
- interfacing with the memory to issue the memory requests in the particular batch to the memory.
A computer readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create a device, comprising:
- a memory controller, comprising:
- a batch unit comprising a plurality of source queues for receiving memory requests from a plurality of sources, each source being associated with a selected one of the source queues, wherein the batch unit is operable to generate batches of memory requests in the source queues;
- a batch scheduler operable to select a batch from one of the source queues;
- and
- a memory command scheduler operable to receive the selected batch from the batch scheduler and issue the memory requests in the selected batch to a memory interfacing with the memory controller.
Dependencies are inferred from the claim text.