Methods of forming contacts for semiconductor devices using a local interconnect processing scheme

A method of forming a local interconnect structure between first and second active regions that are separated by an isolation region, wherein each of said active regions has at least one transistor device formed therein and thereon, the method comprising:

• forming a plurality of dual level source/drain contacts that are each conductively coupled to a source/drain region of one of said at least one transistor device, wherein each of said dual level source/drain contacts is comprised of a lower level source/drain contact and an upper level source/drain contact that is conductively coupled to said lower level source/drain contact, wherein at least one of said lower level source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in said first active region and to a second source/drain region in said second active region;
• forming a patterned mask layer that covers said first and second active regions and exposes at least a portion of said local interconnect structure positioned above said isolation region;
• performing an etching process through said patterned mask layer to remove a portion of said local interconnect structure, said etching process defining a recess positioned above a remaining portion of said local interconnect structure;
• forming an insulating material in said recess;
• and
• forming a gate contact that is conductively coupled to at least one gate electrode of said at least one transistor device, wherein at least a portion of said gate contact is positioned above said insulating material in said recess that is positioned above said remaining portion of said local interconnect structure.

A method of forming a local interconnect structure between first and second active regions that are separated by an isolation region, wherein each of said active regions has at least one transistor device formed therein and thereon, the method comprising:

• forming a plurality of dual level source/drain contacts that are each conductively coupled to a source/drain region of one of said at least one transistor device, wherein each of said dual level source/drain contacts is comprised of a lower level source/drain contact and an upper level source/drain contact that is conductively coupled to said lower level source/drain contact, wherein at least one of said lower level source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in said first active region and to a second source/drain region in said second active region;
• forming a patterned hard mask layer that covers said first and second active regions and exposes a portion of said local interconnect structure that is positioned above said isolation region;
• performing a timed etching process through said patterned mask layer to remove a portion of said local interconnect structure, said etching process defining a recess positioned above a remaining portion of said local interconnect structure, said recess spanning the entirety of said isolation region;
• forming an insulating material in said recess;
• and
• forming a gate contact that is conductively coupled to at least one gate electrode of said at least one transistor device, wherein at least a portion of said gate contact is positioned above said insulating material in said recess that is positioned above said remaining portion of said local interconnect structure.

A method of forming a local interconnect structure between first and second active regions that are separated by an isolation region, wherein each of said active regions has at least one transistor device formed therein and thereon, the method comprising:

• forming a plurality of shared gate electrode structures that are positioned above said first and second active regions and span said isolation region, each of said shared gate electrode structures serving as a gate electrode structure for a transistor formed in and above said first active region and as a gate electrode structure for a transistor formed in and above said second active region;
• forming a plurality of dual level source/drain contacts that are each conductively coupled to a source/drain region of one of said at least one transistor device, wherein each of said dual level source/drain contacts is comprised of a lower level source/drain contact and an upper level source/drain contact that is conductively coupled to said lower level source/drain contact, wherein at least one of said lower level source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in said first active region and to a second source/drain region in said second active region;
• forming a patterned hard mask layer that covers said first and second active regions and exposes a portion of said local interconnect structure that is positioned above said isolation region;
• performing a timed etching process through said patterned mask layer to remove a portion of said local interconnect structure, said etching process defining a recess positioned above a remaining portion of said local interconnect structure, said recess spanning the entirety of said isolation region;
• forming an insulating material in said recess;
• and
• forming a gate contact above said isolation region that is conductively coupled to at least one of said shared gate electrode structures, wherein at least a portion of said gate contact is positioned above said insulating material in said recess that is positioned above said remaining portion of said local interconnect structure.