Signal multiplexing device
AssigneeNippon Telegraph and Telephone Corporation
InventorsHiroaki Katsurai, Hideki Kamitsuna, Yusuke Ohtomo
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Abstract
A signal multiplexing device includes a selector (1) that selects one of input data (4) and a complementary signal (16), a clock recovery circuit (30a) that adjusts the phase of a recovered clock (7) to the timing of the output signal of the selector (1), and a flip-flop circuit (3) that performs identification/recovery of the output signal of the selector (1) based on the recovered clock (7). The frequency of the complementary signal (16) is an integral submultiple of the frequency of the recovered clock (7). The selector (1) selects the complementary signal (16) during part of the no-signal period of the input data (4).
Claims19
A signal multiplexing device comprising:
- a selection circuit that selects and outputs one of an input signal and at least one complementary signal of the input signal;
- a clock recovery circuit that adjusts a phase of a recovered clock to a timing of an output signal of said selection circuit and outputs the recovered clock in synchronism with the output signal of said selection circuit;
- and
- an identification circuit that performs identification/recovery of the output signal of said selection circuit based on the recovered clock,
- wherein a frequency of the recovered clock equals a frequency of the input signal, and a frequency of the complementary signal is an integral submultiple of the frequency of the recovered clock, and
- said selection circuit selects the complementary signal during part of a no-signal period of the input signal.
A signal multiplexing device comprising:
- a clock recovery circuit that adjusts a phase of a recovered clock to a timing of an input signal and outputs the recovered clock in synchronism with the input signal;
- an identification circuit that performs identification/recovery of the input signal based on the recovered clock;
- and
- a selection circuit that selects and outputs one of an output signal of said identification circuit and at least one complementary signal of the output signal,
- wherein a frequency of the recovered clock equals a frequency of the input signal, and a frequency of the complementary signal is an integral submultiple of the frequency of the recovered clock, and
- said selection circuit selects the complementary signal during part of a no-signal period of the input signal.
Dependencies are inferred from the claim text.