US 2013/0294459 A1 · FORWARD ERROR CORRECTION DECODER

Abstract

A method for determining an initial alignment for a frame of input data is provided. A frame for the input data is set, and the frame is synchronized. Specifically, a syndrome check of the frame is performed using a first predetermined number of bits, and a slip of a second predetermined number of bits is requested following the syndrome check. Evaluation of the syndrome check to determine whether the frame is aligned can then be performed in parallel with the slipping. The evaluation and slipping can then be repeated if the frame is misaligned. When the frame is aligned, a lock condition can be indicated, and the slip performed in parallel with the evaluation indicating that the frame is aligned can be deasserted. In addition, when the frame is aligned, error correction on the frame can be performed, and the error corrected frame can be formatted.

Claims20

Dependent claims

A method comprising:

receiving input data;
setting a frame for the input data;
synchronizing the frame by:
performing a syndrome check of the frame using a first predetermined number of bits;
requesting a slip of a second predetermined number of bits following the step of performing;
evaluating the syndrome check in parallel with the step of requesting to determine whether the frame is aligned;
repeating the steps of performing and evaluating if the frame is misaligned;
and
when the frame is aligned, indicating a lock condition;
and
when the frame is aligned, deasserting the slip performed in parallel with the evaluation indicating that the frame is aligned;
performing error correction on the frame that is aligned to generate an error corrected frame;
and
formatting the error corrected frame.

11 more elements

An apparatus comprising:

physical medium dependant (PMD) sublayer logic that is configured to communicate with a communications medium;
PMA sublayer logic that is coupled to the PMD logic;
PCS sublayer logic that is configured to communicate with an interface;
and
forward error correction (FEC) sublayer logic having:
an encoder that is coupled to the PMA sublayer logic;
and
a decoder having:
a framer that is coupled to the PMA sublayer logic so as to receive input data, wherein the framer is configured to set a frame for the input data;
a syndrome generator that is coupled to the framer, wherein the syndrome generator is configured to perform a syndrome check of the frame using a first predetermined number of bits, and wherein the syndrome generator is configured to request a slip of a second predetermined number of bits by the framer following the syndrome check;
a lock state machine that is coupled to the syndrome generator and the framer, wherein the lock state machine is configured to evaluate the syndrome check in parallel with the slip to determine whether the frame is aligned, and wherein the lock state machine is configured to indicate a lock condition when the frame is aligned, and wherein the lock state machine is configured to request deassertion of the slip performed in parallel with the evaluation indicating that the frame is aligned;
an error correction circuit that is coupled to the lock state machine and the syndrome generator;
and
a formatter that is coupled to the error correction circuit and the PCS sublayer logic.

11 more elements

An apparatus comprising:

a communications medium;
a plurality of network interfaces, wherein each network interface includes:
a media access control (MAC) circuit;
a media independent interface (MII) that is coupled to the MAC circuit;
and
a physical transceiver (PHY) having:
PMD sublayer logic that is configured to communicate with a communications medium;
PMA sublayer logic that is coupled to the PMD logic;
PCS sublayer logic that is coupled to the MII;
and
FEC sublayer logic having:
an encoder that is coupled to the PMA sublayer logic;
and
a decoder having:
a framer that is coupled to the PMA sublayer logic so as to receive input data, wherein the framer is configured to set a frame for the input data;
a syndrome generator that is coupled to the framer, wherein the syndrome generator is configured to perform a syndrome check of the frame using a first predetermined number of bits, and wherein the syndrome generator is configured to request a slip of a second predetermined number of bits by the framer following the syndrome check;
a lock state machine that is coupled to the syndrome generator and the framer, wherein the lock state machine is configured to evaluate the syndrome check in parallel with the slip to determine whether the frame is aligned, and wherein the lock state machine is configured to indicate a lock condition when the frame is aligned, and wherein the lock state machine is configured to request deassertion of the slip performed in parallel with the evaluation indicating that the frame is aligned;
an error correction circuit that is coupled to the lock state machine and the syndrome generator;
and
a formatter that is coupled to the error correction circuit and the PCS sublayer logic.

17 more elements

Dependencies are inferred from the claim text.

Forward error correction decoder

Life of this patent

Forward error correction decoder

Life of this patent

Abstract

Claims20