Systems, processes and integrated circuits for improved packet scheduling of media over packet
AssigneeTexas Instruments Incorporated
InventorAndrew W. Welin
Life of this patent
Estimating the term…
Abstract
A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
Claims7
A method of processing a packet stream of arriving packets having packetized information, comprising:
- A. detecting whether the arriving packets are respectively voice packets or silence packets;
- B. queuing information from the voice packets;
- C. decoding information from the voice packets to produce decoded voice information;
- D. post-processing information from the silence packets;
- and
- E. buffering the decoded voice information from the voice packets interspersed with post-processed information from the silence packets.
A single-chip integrated circuit comprising:
- A. a processor circuit;
- and
- B. embedded electronic instructions operating in the processor circuit including:
- i. an egress packet control engine that detects whether the arriving packets are respectively voice packets or silence packets,
- ii. queues information from the voice packets and produces decoded voice information,
- iii. post-processes the silence packets, and
- iv. buffers the decoded voice information from the voice packets interspersed with post-processed silence packets.
Dependencies are inferred from the claim text.