Memory device for performing multi-core access to bank groups

A system comprising a memory device, and a memory controller controlling the memory device and configured to interface with a host device, wherein the memory device has a burst length “b”, performs “k” core accesses per command, and receives a command from the memory controller, where “b” is an integer of at least 2 and “k” is an integer of at least 2 and at most “b”, and wherein the memory device comprises:

• a memory cell array comprising a plurality of bank groups;
• a plurality of bank group control units respectively corresponding to the plurality of bank groups, each of the bank group control units configured to generate a multiplexer control signal for selecting part of data read from a corresponding bank group;
• and
• a multiplexer configured to sequentially output data read from the plurality of bank groups according to the multiplexer control signal output from the plurality of bank group control units,
• wherein data items comprised in output data of the multiplexer have a same time space.