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US 2013/0294173 A1Published application
Method and apparatus for the erase suspend operation
AssigneeMacronix International Co., Ltd.
InventorsChuan-Ying Yu, Ken-Hui Chen, Chun-Hsiung Hung, Kuen-Long Chang
Life of this patent
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Abstract
Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.
Claims21
An apparatus, comprising:
- a memory array including a plurality of memory cells arranged in a plurality of sectors including at least a first sector accessed by at least a first word line and a second sector accessed by at least a second word line;
- and
- control logic responsive to a non-erase command, by applying a negative voltage to the first word line and a non-negative voltage to the second word line.
A method, comprising:
- receiving a non-erase command at control logic in an integrated circuit with memory;
- and
- responsive to the received non-erase command, the control logic applying (i) a negative voltage to a first word line accessing a first set of memory cells in a first sector of the memory, and (ii) a non-negative voltage to a second word line accessing a second set of memory cells in a second sector of the memory.
Dependencies are inferred from the claim text.