Non-volatile semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorMasanobu SHIRAKAWA
Life of this patent
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Abstract
According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality of physical blocks. Each of the plurality of physical blocks includes a plurality of string units. Each string unit has a plurality of NAND strings that shares a plurality of word lines connected to a plurality of memory cells, respectively. The memory region is disposed to one of the plurality of physical blocks. Each of the plurality of string units configures a first logical block, and when the first logical block is failed, information of the first failed logical block is stored in a first region of the memory region.
Claims19
A non-volatile semiconductor memory device comprising:
- a memory cell array comprising a plurality of physical blocks, each of the plurality of physical blocks comprising a plurality of string units, and each string unit comprising a plurality of NAND strings that share a plurality of word lines connected to a plurality of memory cells, respectively;
- and
- a memory region disposed to one of the physical block,
- wherein each of the string units configures a first logical block, and when the first logical block has a failure, the information of the first failed logical block is stored in a first region of the memory region.
A non-volatile semiconductor memory device comprising:
- a memory cell array comprising a plurality of physical blocks disposed in the direction of a plurality of bit lines;
- a plurality of string units disposed to each of the plurality of physical blocks in the direction of the bit lines, each of the string units comprising first, second, and third word line groups that share first, second, and third selection gate lines;
- and
- a memory region disposed to one of the plurality of physical blocks,
- wherein each of the first, second, and third word line groups comprises a plurality of word lines stacked on a semiconductor substrate, the plurality of word lines being disposed in a direction orthogonal to the plurality of bit lines;
- and
- the first, second, and third selection gate lines are disposed on the first, second, and third word line groups;
- and
- each of the string units configures a logical block, and when the logical block has a failure, the information of the failed logical block is stored in the memory region.
Dependencies are inferred from the claim text.