Erase Inhibit For 3D Non-Volatile Memory

A method for performing an erase operation in a 3D stacked non-volatile memory device, comprising:

• performing a two-sided erase for a plurality of NAND strings, each NAND string comprises a plurality of memory cells between a drain end of the NAND string and a source end of the memory string;
• determining when one or more NAND strings of the plurality of NAND strings pass an erase-verify test;
• and
• when the one or more NAND strings of the plurality of NAND strings pass the erase- verify test, switch to performing a one-sided erase for remaining NAND strings of the plurality of NAND strings which have not yet passed the erase-verify test.

A 3D stacked non-volatile memory device, comprising:

• a substrate;
• a stacked non-volatile memory cell array carried by the substrate, and comprising a plurality of NAND strings, each NAND string comprises a drain end and a source end, and the plurality of NAND strings are arranged in sub-blocks, where the NAND strings in each sub-block have their source ends connected to a common source line of the sub-block;
• a plurality of bit lines connected to the drain ends of the NAND strings;
• and
• at least one control circuit in communication with the stacked non-volatile memory cell array, the plurality of bit lines and the source lines, the at least one control circuit, to perform an erase operation, performs a two-sided erase for the plurality of NAND strings until one or more NAND strings of the plurality of NAND strings pass an erase-verify test, and, when the one or more NAND strings of the plurality of NAND strings pass the erase-verify test, switches to performing a one-sided erase for remaining NAND strings of the plurality of NAND strings which have not yet passed the erase-verify test.