Flash-based memory system with robust backup and restart features and removable modules

A method of testing a Flash-based memory system having a backup power source, comprising:

• providing power to the Flash-based memory system, the power being provided from a primary power source during normal operation of the Flash-based memory system and from a backup power source when the primary power source falls below a predefined level, the backup power source including a charge storage device and charging circuitry configured to charge the charge storage device;
• automatically performing one or more test procedures on the charge storage device and providing an indication of a charge storage capacity of the charge storage device, the one or more test procedures comprising:
• disabling the charging circuitry from charging the charge storage device;
• obtaining a first voltage measurement from the charge storage device;
• applying a predefined load to the charge storage device;
• obtaining a second voltage measurement from the charge storage device;
• waiting a predefined amount of time;
• and
• obtaining a third voltage measurement from the charge storage device;
• wherein providing an indication of the charge storage capacity of the charge storage device comprises providing at least one of a capacitance C of the charge storage device and an equivalent series resistance (ESR) of the charge storage device based on one or more of the first, second, and third voltage measurements.

A Flash-based memory system having a backup power source, comprising:

• a plurality of Flash memory devices;
• a Flash controller communicating independently with each Flash memory device;
• a backup power source providing power to the Flash memory devices when a primary power source falls below a predefined level, the backup power source including a charge storage device;
• and
• a central processing unit (CPU) coupled to the backup power source, the CPU configured to perform one or more predefined test procedures on the charge storage device and provide an indication of a charge storage capacity of the charge storage device, the CPU providing the indication of the charge storage capacity of the charge storage device by providing at least one of a capacitance C of the charge storage device and an equivalent series resistance (ESR) of the charge storage device.