Column Redundancy Circuitry for Non-Volatile Memory

A method of operating a memory circuit having an array of non-volatile memory cells formed along a plurality of word lines and a plurality of columns:

• generating from an input clock signal a corresponding series of a first plurality of sequential non-overlapping of output clocks signals;
• receiving a series of data;
• and
• in response to the corresponding one of the output clock signals, transferring a first number of bits from the series of data to a corresponding first set of access circuits each connected to the columns of a corresponding first plurality of divisions of the memory array and sequentially accessing columns of the corresponding one of the divisions,
• wherein each division is formed of a plurality of contiguous columns of the memory array, where the word lines span all of the columns of the array.

A method of operating a memory circuit having an array of non-volatile memory cells form along a plurality of word lines and a plurality of columns:

• generating from an input clock signal a corresponding series of a first plurality of sequential non-overlapping of output clocks signals;
• in response to the corresponding one of the output clock signals, sequentially accessing columns of a corresponding first plurality of divisions of the memory array and transferring a first number of bits from a corresponding first set of access circuits each connected to the columns of a corresponding one of the divisions to one or more data buses to form a series of data;
• and
• transferring out the series of data on the data bus,
• wherein each division is formed of a plurality of contiguous columns of the memory array, where the word lines span all of the columns of the array.