Plural operation of memory device

An integrated circuit device, comprising:

• a memory array comprising memory cells, configurable to store data for a first pattern of data usage in response to a first operation algorithm, and to store data for a second pattern of data usage in response to a second operation algorithm, wherein the first pattern of data usage includes a first rate of data cycling, and the second pattern of data usage includes a second rate of data cycling, the second rate being higher than the first rate;
• controller circuitry coupled to the memory array, and configured to execute the first and second operation algorithms in respective first and second blocks of memory cells in the memory array, wherein a word line pass voltage applied in the first operation algorithm is at a lower voltage level than a second word line pass voltage applied in the second operation algorithm, the first and second blocks are distinguishable by block boundaries including a high block boundary and a low block boundary, the first memory block including memory cells at addresses within a range between the high block boundary and the low block boundary.