Memory device including antifuse memory cell array and memory system including the memory device

A memory device comprising:

• a memory cell array comprising a plurality of sub arrays, each of the sub arrays comprising a plurality of antifuse memory cells arranged in rows and columns and electrically coupled to a plurality of bit lines and a plurality of word lines;
• a column decoder configured to output a plurality of bit line selection signals, and to select one bit line among the bit lines in response to one of the bit line selection signals;
• a first row decoder configured to output a first word line selection signal and to select a first word line in response to the first word line selection signal, the first row decoder electrically coupled to a first set of antifuse memory cells arranged in a first row and a third row;
• a second row decoder configured to output a second word line selection signal and to select a second word line in response to the second word line selection signal, the second row decoder electrically coupled to a second set of antifuse memory cells arranged in a second row and a fourth row;
• and
• a sense amplifier configured to sense and amplify data of a selected antifuse memory cell,
• wherein the second row is arranged between the first and third rows.

An antifuse device comprising:

• an antifuse memory cell array comprising a plurality of antifuse memory cells arranged in rows and columns and electrically coupled to a plurality of bit lines and a plurality of word lines;
• a column decoder configured to be electrically coupled to the bit lines, to output a plurality of bit line selection signals, and to select one bit line among the bit lines in response to one of the bit line selection signals;
• and
• a row decoder comprising:
• a first word line driver configured to output a first word line selection signal, the first word line driver electrically coupled to a first set of antifuse memory cells arranged in first and third rows;
• and
• a second word line driver configured to output a second word line selection signal, the second word line driver electrically coupled to a second set of antifuse memory cells arranged in second and fourth rows,
• wherein the third row is arranged between the second row and the fourth row,
• wherein a first bit line electrically coupled to the antifuse memory cell array is connected to a third set of antifuse memory cells arranged in a first column, and
• wherein the third set of antifuse memory cells includes at least one antifuse memory cell of each of the first and second set of antifuse memory cells.