Image data compression using stacked-chip image sensors
AssigneeAptina Imaging Corporation
InventorsBrian Keelan, Dhandapani Dharumalingam
Life of this patent
Estimating the term…
Loading patent…
AssigneeAptina Imaging Corporation
InventorsBrian Keelan, Dhandapani Dharumalingam
Estimating the term…
Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels and processing circuitry. The image pixel array may be coupled to the processing circuitry through an array of vertical metal interconnects. The image pixel array may be partitioned into image pixel sub-arrays configured to capture image data at a capture frame rate. The processing circuitry may compress image data associated with each image pixel sub-array in parallel and may output the compressed image data to off-chip image processing circuitry at an output frame rate that is less than the capture frame rate. The processing circuitry may determine respective compression block sizes for each image pixel sub-array with which to compress the associated image data and may determine respective output frame rates for image data from each image pixel sub-array.
A method for operating a stacked-chip image sensor having a planar array of image pixels and storage and processing circuitry that is vertically displaced from the planar array of image pixels in a direction that is perpendicular to the planar array of image pixels, wherein the planar array of image pixels includes a plurality of image pixel sub-arrays, the method comprising:
A method for operating a stacked-chip image sensor that is coupled to off-chip image processing circuitry, wherein the stacked-chip image sensor comprises a planar array of image sensor pixels, an array of conductive vias, and processing circuitry, the method comprising:
A system, comprising:
Dependencies are inferred from the claim text.