US 2013/0293273 A1 · DETECTION OF FAST SUPPLY RAMP IN RESET CIRCUIT

Abstract

A method for generating a reset signal in a system on a chip (SoC) is disclosed. A sense signal is generated responsive to a supply voltage provided to the SoC. A reset signal is asserted while the sense signal is below a threshold voltage level. The sense signal may be forced below the threshold value for a period of time determined by a first capacitive time constant circuit. Operation of the first capacitive time constant circuit is inhibited after the sense signal has been above the threshold value level for a second period of time as determined by a second capacitive time constant circuit responsive to the supply voltage. In some embodiments, the first capacitive time constant circuit and the second capacitive time constant circuit may be discharged when the supply voltage falls below a second threshold voltage level, such that the reset signal is again asserted.

Claims17

Dependent claims

A method for generating a reset signal in a system on a chip (SoC), the method comprising:

generating a sense signal responsive to a supply voltage provided to the SoC;
asserting a reset signal while the sense signal is below a threshold voltage level and releasing the reset signal while the sense signal is above the threshold voltage level;
forcing the sense signal below the threshold value for a period of time determined by a first capacitive time constant circuit responsive to a rise in the supply voltage;
and
inhibiting operation of the first capacitive time constant circuit after the sense signal has been above the threshold value level for a second period of time as determined by a second capacitive time constant circuit responsive to the supply voltage.

2 more elements

A system on a chip (SOC), comprising:

a supply buss and a reference plane;
a reset circuit coupled between the supply buss and to the reference plane, the reset circuit comprising:
a sense circuit operable to generate a sense signal responsive to a supply voltage provided to the SoC on the supply buss;
a detection circuit operable to assert a reset signal while the sense signal is below a threshold voltage level and to release the reset signal while the sense signal is above the threshold voltage level;
a capacitive coupled rate detection circuit coupled between the supply buss and the reference plane with an output controllably coupled to the sense circuit, operable to force the sense signal below the threshold value for a period of time responsive to a rise in the supply voltage;
and
a capacitive coupled timing circuit coupled between the supply buss and the reference plane with an output controllably coupled to the first capacitive timing circuit, operable to inhibit operation of the capacitive coupled rate detection circuit after the sense signal has been above the threshold value level for a second period of time responsive to the supply voltage.

4 more elements

Dependencies are inferred from the claim text.

Detection of fast supply ramp in reset circuit

Life of this patent

Detection of fast supply ramp in reset circuit

Life of this patent

Abstract

Claims17