# US 2013/0280902 A1 · Stratified gate dielectric stack for gate dielectric leakage reduction

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- Number: US 2013/0280902 A1
- Document ID: US20130280902A1
- Status: Published application
- Kind: A1
- Application number: 13/449,647
- Filed: 2012-04-18
- Published: 2013-10-24
- Earliest claimed: 2012-04-18
- Assignees: International Business Machines Corporation
- Inventors: Hemanth Jagannathan; Paul C. Jamison
- Web page: https://patentgrep.com/patent/US20130280902A1

## CPC

- H10P 14/40: of conductive or resistive materials
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/01332: {Making the insulator}
- H10D 64/01344: {in a nitrogen-containing ambient, e.g. N2O oxidation}
- H10D 64/01346: {in a gaseous ambient using an oxygen or a water vapour, e.g. oxidation through a layer (H10D64/01344 takes precedence)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness.

## Claims

### Claim 1

A method of forming a semiconductor structure including a field effect transistor (FET), said method comprising:
forming a first high dielectric constant (high-k) gate dielectric layer comprising a first high-k dielectric material and located on a semiconductor substrate;
forming a band-gap-disrupting dielectric layer comprising a dielectric material having a different band gap than said first high-k gate dielectric on said first high-k gate dielectric layer;
forming a second high-k gate dielectric layer comprising a second high-k dielectric material having a different band gap than said band-gap-disrupting dielectric of said band-gap-disrupting dielectric layer; and
patterning a stack of said first high-k gate dielectric layer, said band-gap-disrupting dielectric layer, and said second high-k gate dielectric layer to form a stratified gate dielectric stack of a first high-k gate dielectric, a band-gap-disrupting dielectric, and a second high-k gate dielectric, wherein a first atomic interface between said band-gap-disrupting dielectric and said first high-k gate dielectric is spaced from a second atomic interface between said band-gap-disrupting dielectric and said second high-k gate dielectric by at least one continuous atomic layer of said dielectric material of said band-gap-disrupting dielectric within said stratified gate dielectric stack.

### Claim 2 (depends on 1)

The method of claim 1, wherein said forming of said stratified gate dielectric stack comprises preserving said first high-k dielectric material to be substantially free of said dielectric material of said band-gap-disrupting dielectric until, and during, said patterning of said stack.

### Claim 3 (depends on 2)

The method of claim 2, wherein said forming of said stratified gate dielectric stack further comprises preserving said second high-k dielectric material to be substantially free of said dielectric material of said band-gap-disrupting dielectric until, and during, said patterning of said stack.

### Claim 4 (depends on 3)

The method of claim 3, wherein said forming of said stratified gate dielectric stack further comprises preserving said dielectric material of said band-gap-disrupting dielectric to be substantially free of said first high-k dielectric material and said second high-k dielectric material until, and during, said patterning of said stack.

### Claim 5 (depends on 1)

The method of claim 1, wherein said forming of said band-gap-disrupting dielectric layer comprises depositing a material selected from La2O3, Al2O3, TiO2, La2OuNv, Al2OuNv, TiOuNv, and an alloy thereof, wherein each value of u is independently from 0.5 to 3 and each value of v is independently from 0 to 2.

### Claim 6 (depends on 5)

The method of claim 5, wherein said forming of said first high-k gate dielectric layer comprises depositing a material selected from HfO2, ZrO2, HfOxNy, ZrOxNy, and alloys thereof, wherein each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.

### Claim 7 (depends on 6)

The method of claim 6, wherein said forming of said second high-k gate dielectric layer comprises depositing a same material as said first high-k dielectric material as said second high-k dielectric material.

### Claim 8 (depends on 6)

The method of claim 6, wherein said forming of said second high-k gate dielectric layer comprises depositing a material having a different composition from a composition of said first high-k dielectric material and selected from HfO2, ZrO2, HfOpNq, ZrOpNq, and alloys thereof, wherein each value of p is independently from 0.5 to 3 and each value of q is independently from 0 to 2.

### Claim 9 (depends on 1)

The method of claim 1, further comprising forming a gate cavity laterally surrounded by a planarization dielectric layer on a semiconductor substrate, wherein each of said first high-k gate dielectric layer, said band-gap-disrupting dielectric layer, and said second high-k gate dielectric layer are sequentially deposited within said gate cavity.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a disposable gate structure on said semiconductor substrate prior to forming said planarization dielectric layer; and
planarizing said planarization dielectric layer, wherein a topmost surface of said disposable gate structure is coplanar with a top surface of said planarization dielectric layer after said planarizing, and said gate cavity is formed by removing said disposable gate structure after said planarizing of said planarization dielectric layer.

### Claim 11 (depends on 9)

The method of claim 9, wherein said patterning of said stack of said first high-k gate dielectric layer, said band-gap-disrupting dielectric layer, and said second high-k gate dielectric layer comprises removing portions of said first high-k gate dielectric layer, said band-gap-disrupting dielectric layer, and said second high-k gate dielectric layer from above a top surface of said planarization dielectric layer.

### Claim 12 (depends on 9)

The method of claim 9, further comprising:
forming a work function material layer on said second high-k dielectric layer and within said gate cavity;
forming a conductive material layer on said work function material layer and within said gate cavity; and
removing portions of said work function material layer and said conductive material layer from above a planarized surface of said planarization dielectric layer.

### Claim 13 (depends on 9)

The method of claim 9, further comprising forming a gate spacer on sidewalls of said disposable gate structure, wherein said first high-k gate dielectric layer is deposited directly on inner sidewalls of said gate spacer.

### Claim 14 (depends on 1)

The method of claim 1, further comprising maintaining said stratified gate dielectric stack under a temperature that induces detectable interdiffusion of materials across said first atomic interface or said second atomic interface at least until at least said field effect transistor is incorporated into a functional semiconductor chip.

### Claim 15 (depends on 1)

The method of claim 1, further comprising forming an additional high-k gate dielectric layer directly on said second high-k gate dielectric layer, said additional high-k gate dielectric layer comprising an additional high-k dielectric material different from said second high-k dielectric material and selected from La2O3, Al2O3, TiO2, HfO2, ZrO2, La2OsNt, Al2OsNt, TiOxNt, HfOsNt, ZrOsNt and an alloy thereof, wherein each value of s is independently from 0.5 to 3 and each value of t is independently from 0 to 2.

### Claim 16 (depends on 1)

The method of claim 1, further comprising forming an additional high-k gate dielectric layer directly on said semiconductor substrate, said additional high-k gate dielectric layer comprising an additional high-k dielectric material different from said first high-k dielectric material and selected from La2O3, Al2O3, TiO2, HfO2, ZrO2, La2Os′Nt′, Al2Os′Nt′, TiOs′Nt′, HfOs′Nt′, ZrOs′Nt′ and an alloy thereof, wherein each value of s′ is independently from 0.5 to 3 and each value of t′ is independently from 0 to 2.

### Claim 17 (depends on 1)

The method of claim 1, wherein said band-gap-disrupting dielectric layer is formed by a substantially conformal deposition method that forms said band-gap-disrupting dielectric layer as a single contiguous layer.

### Claim 18 (depends on 1)

The method of claim 1, wherein said band-gap-disrupting dielectric layer is formed by a non-conformal deposition method that forms said band-gap-disrupting dielectric layer as at least two disjoined portions including an upper portion overlying a planarization dielectric layer and a lower portion located underneath a top surface of said planarization dielectric layer.

### Claim 19 (depends on 18)

The method of claim 18, wherein a vertical portion of said second high-k gate dielectric layer is deposited directly on a sidewall of said first high-k gate dielectric layer.

### Claim 20 (depends on 1)

The method of claim 1, further comprising forming an interfacial dielectric by converting a surface portion of a semiconductor material of said semiconductor substrate into a dielectric material comprising said semiconductor material and at least one of oxygen and nitrogen.

### Claim 21 (depends on 1)

The method of claim 1, wherein said semiconductor substrate is a bulk semiconductor substrate and said field effect transistor is a planar field effect transistor.

### Claim 22 (depends on 1)

The method of claim 1, wherein said semiconductor substrate is a semiconductor-on-insulator substrate and said field effect transistor is a planar field effect transistor.

### Claim 23 (depends on 1)

The method of claim 1, wherein said semiconductor substrate comprises a semiconductor fin formed on a bulk semiconductor substrate.

### Claim 24 (depends on 1)

The method of claim 1, wherein said semiconductor substrate comprises a semiconductor fin formed on a stack, from bottom to top, of a handle substrate and a buried insulator layer.

### Claim 25 (depends on 1)

The method of claim 1, further comprising forming a gate spacer directly on sidewalls of each of said first high-k dielectric, said band-gap-disrupting dielectric, and said second high-k dielectric.