# US 2013/0280889 A1 · Semiconductor device and method capable of scribing chips with high yield > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0280889 A1 - Document ID: US20130280889A1 - Status: Published application - Kind: A1 - Application number: 13/922,244 - Filed: 2013-06-20 - Published: 2013-10-24 - Earliest claimed: 2003-04-30 - Assignees: Fujitsu Semiconductor Limited - Applicants: Fujitsu Semiconductor Limited - Inventors: Satoshi OTSUKA - Web page: https://patentgrep.com/patent/US20130280889A1 ## CPC - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 20/031: {of conductive parts of the interconnections} - H10W 20/071: {of dielectric parts thereof} - H10W 20/092: {by smoothing the dielectric parts} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 72/019: {of bond pads} - H10W 20/085: {involving intermediate temporary filling with material} - H10W 20/087: {involving multiple stacked pre-patterned masks} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/59: Bond pads specially adapted therefor - H10W 72/9232: {with additional elements interposed between layers} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/983: {Reinforcing structures, e.g. collars} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device comprising scribe areas that include dicing areas for separating chip areas, a groove forming area surrounding each chip area, and includes interlayer insulating lamination disposed above the semiconductor wafer; a multilayer wiring structure formed in the interlayer insulating lamination, the multilayer wiring structure including wiring layers disposed in the chip area, and dummy wirings disposed in the chip area and the scribe area, the wiring layers and the dummy wirings being formed from same mother layers; a cover layer including a passivation layer, the cover layer covering the multilayer wiring structure; and a groove formed in each groove forming area, the groove surrounding the chip areas and extending from a surface of the semiconductor wafer and at least through the passivation layer; wherein the multilayer wiring structure includes no dummy wirings in the groove forming area at least in an uppermost wiring layer. ## Claims ### Claim 1 A semiconductor device fabrication method comprising the steps of: (a) preparing a semiconductor wafer having a plurality of chip areas formed with semiconductor elements and a scribe area having a dicing area in said scribe area for separating said plurality of chip areas, wherein in said scribe area a groove forming area is defined to surround each chip area at a position outside of the dicing area; (b) disposing a multilayer wiring structure including dummy wirings above said semiconductor wafer, said multilayer wiring structure having interlayer insulating films and wiring layers alternately formed; (c) forming a cover layer including a passivation layer, said cover layer covering said multilayer wiring structure; and (d) forming a groove in each said groove forming area, said groove surrounding each of said plurality of chip areas and extending from a surface of said semiconductor wafer and at least through said passivation layer. ### Claim 2 (depends on 1) The semiconductor device fabrication method according to claim 1, wherein at least in an uppermost wiring layer in said groove forming area said step (b) does not form a dummy wiring. ### Claim 3 (depends on 1) The semiconductor device fabrication method according to claim 1, wherein said wiring layer includes a copper wiring layer. ### Claim 4 (depends on 1) The semiconductor device fabrication method according to claim 1, further comprising the step of: (e) after said step (d), dicing said semiconductor wafer in said dicing area. ### Claim 5 (depends on 1) The semiconductor device fabrication method according to claim 1, wherein at least an uppermost wiring layer does not include a dummy wiring in said scribe area, and an underlying wiring layer includes said dummy wirings in an area other than said groove forming area. ### Claim 6 (depends on 5) The semiconductor device fabrication method according to claim 5, wherein said uppermost wiring layer is an aluminum wiring layer. ### Claim 7 (depends on 6) The semiconductor device fabrication method according to claim 6, wherein wiring layers of said multilayer wiring structure other than said uppermost wiring layer are copper wiring layers of a damascene structure. ### Claim 8 (depends on 7) The semiconductor device fabrication method according to claim 7, wherein said interlayer insulating films on said copper wiring layers include a copper diffusion preventive layer capable of preventing copper diffusion and an insulating layer formed on said copper diffusion preventive layer. ### Claim 9 (depends on 1) The semiconductor device fabrication method according to claim 1, wherein an uppermost wiring layer of said multilayer wiring structure includes a pad, said step (d) includes an etching step of selectively removing said cover layer to expose said pad and selectively removing said cover layer and an underlying interlayer insulating film in said groove forming area. ### Claim 10 (depends on 1) The semiconductor device fabrication method according to claim 1, wherein said groove has a generally rectangular loop shape whose corners are cut off at a position outside of each corner of said chip area. ### Claim 11 (depends on 1) The semiconductor device fabrication method according to claim 1, wherein a width of said groove forming area is one third of or narrower than a width of said scribe area. ### Claim 12 (depends on 1) The semiconductor device fabrication method according to claim 1, wherein a width of said groove is in a range from 0.5 μm to 10 μm.