# US 2013/0280877 A1 · Methods for fabricating high voltage field effect transitor finger terminations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0280877 A1 - Document ID: US20130280877A1 - Status: Published application - Kind: A1 - Application number: 13/795,986 - Filed: 2013-03-12 - Published: 2013-10-24 - Earliest claimed: 2012-04-18 - Assignees: RF Micro Devices, Inc. - Applicants: Rf Micro Devices, Inc. - Inventors: Kevin Wesley Kobayashi; Haldane S. Henry; Andrew P. Ritenour - Web page: https://patentgrep.com/patent/US20130280877A1 ## CPC - H10D 64/111: {Field plates} - H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT} - H10D 30/021: {of FETs having insulated gates [IGFET]} - H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs} - H10D 30/80: FETs having rectifying junction gate electrodes (H10D30/40 takes precedence) - H10D 30/87: FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] {(FETs having Schottky contact on top of heterojunction gate H10D30/801)} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/251: {Source or drain electrodes for field-effect devices} - H10D 64/411: {for FETs} - H10D 62/8325: {Silicon carbide} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation. ## Claims ### Claim 1 A method comprising: providing a field effect transistor structure disposed on a substrate, the field effect transistor structure comprising; a buffer layer disposed on the substrate; a device layer disposed on the buffer layer; a cap layer disposed on the device layer; and a passivation layer disposed on the cap layer; and etching at least one gate channel into the passivation layer wherein at least one side of the at least one gate channel is inclined downwardly towards the cap layer with a predetermined slope that reduces electric fields at a gate edge by a predetermined amount. ### Claim 2 (depends on 1) The method of claim 1 further comprising implanting a predetermined number of ions into a periphery of the field effect transistor structure to provide electrical isolation for the field effect transistor structure. ### Claim 3 (depends on 1) The method of claim 1 further comprising etching a mesa around a periphery of the field effect transistor structure to provide electrical isolation for the field effect transistor structure. ### Claim 4 (depends on 1) The method of claim 1 wherein the buffer layer is made of gallium nitride (GaN). ### Claim 5 (depends on 1) The method of claim 1 wherein the device layer is made of aluminum gallium nitride/GaN (AlGaN/GaN). ### Claim 6 (depends on 1) The method of claim 1 wherein the device layer is made of GaN. ### Claim 7 (depends on 1) The method of claim 1 wherein the cap layer is made of GaN. ### Claim 8 (depends on 1) The method of claim 1 wherein the passivation layer is made of a high breakdown dielectric material. ### Claim 9 (depends on 8) The method of claim 8 wherein the high breakdown dielectric material is silicon nitride (SiN). ### Claim 10 (depends on 1) The method of claim 1 wherein the predetermined slope that reduces the electric fields at the gate edge by a predetermined amount provides a gate leakage current that is less than around about 10 μA/mm for a drain-to-source voltage that ranges from around about 500 V to around about 1200 V. ### Claim 11 (depends on 1) The method of claim 1 further including providing at least one source finger in contact with an active region, at least one gate finger in rectifying contact with the active region, and at least one drain finger in contact with the active region. ### Claim 12 (depends on 11) The method of claim 11 further including providing a source field plate integral with the at least one source finger such that the at least one side extends downwardly towards the active region between the at least one gate finger and the at least one drain finger. ### Claim 13 (depends on 11) The method of claim 11 further including providing a gate field plate integrated with the at least one gate finger. ### Claim 14 (depends on 13) The method of claim 13 wherein the gate field plate integrated with the at least one gate finger appears as a T shape or alternatively a Γ shape when viewed from an end of the at least one gate finger. ### Claim 15 (depends on 11) The method of claim 11 further including providing the at least one gate finger with chamfered ends. ### Claim 16 (depends on 11) The method of claim 11 further including providing the at least one gate finger with rounded ends. ### Claim 17 (depends on 11) The method of claim 11 wherein the at least one gate finger has an end with a sloped foot. ### Claim 18 (depends on 17) The method of claim 17 wherein the sloped foot inclines downwardly towards the substrate. ### Claim 19 (depends on 11) The method of claim 11 wherein at least one end of the at least one gate finger extends outside of the active region. ### Claim 20 (depends on 11) The method of claim 11 wherein the at least one gate finger is confined within the active region.