Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage

A semiconductor integrated device, comprising:

• a peripheral circuit that includes a first transistor having a gate oxide film, said peripheral circuit being supplied with a first power supply voltage;
• and
• a semiconductor memory circuit,
• wherein said semiconductor memory circuit includes;
• a plurality of word lines;
• a plurality of memory cells, each of which has a gate transistor, said gate transistor having a gate electrode and a gate oxide film, said gate oxide film having substantially the same thickness as the gate oxide film of the first transistor;
• a pair of bit lines coupled to a plurality of memory cells;
• a precharge circuit precharging said pair of bit lines to a precharge voltage, and having a second transistor coupled to said pair of bit lines, said second transistor having a oxide with substantially the same thickness as the gate oxide film of the first transistor;
• a sense amplifier circuit coupled between said pair of bit lines and amplifying a difference in potential between said pair of bit lines;
• a first driver circuit driving said word lines so as to alternately provide the gate electrode of said gate transistor with a first voltage and a second voltage which is lower than said first voltage, and
• a second driver circuit driving a precharge control line so as to alternately provide the gate electrode of said second transistor with said first voltage and a third voltage which is lower than said first voltage,
• wherein said first voltage is higher than said first power supply voltage.

A semiconductor integrated device comprising:

• a word line;
• a word line driver coupled to the word line and alternately providing to the word line a first voltage and a second voltage lower than the first voltage;
• a pair of bit lines;
• a dynamic type memory cell including:
• a capacitance and
• a first MOS transistor having a gate coupled to the word line and a source-drain path coupled between one of the pair of bit lines and one end of the capacitance and being in an ON state when the word line is of the first voltage, the first MOS transistor further having a first gate oxide film;
• a sense amplifier coupled to the pair of bit lines and including a second MOS transistor having a gate coupled to one of the pair of bit lines and a second gate oxide film;
• a precharge circuit coupled to the pair of bit lines and including a third MOS transistor having a gate and a third gate oxide film;
• a precharge control line coupled to the gate of the second MOSFET;
• a precharge control line driver coupled to the precharge control line and providing to the precharge control line the first voltage or a third voltage;
• an address decoder coupled to the word line driver and having a fourth MOS transistor having a gate and a fourth gate oxide film;
• wherein the first, second, third and fourth oxide films have substantially the same thickness.