# US 2013/0279255 A1 · Semiconductor memory device and method for controlling the same

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- Number: US 2013/0279255 A1
- Document ID: US20130279255A1
- Status: Published application
- Kind: A1
- Application number: 13/843,321
- Filed: 2013-03-15
- Published: 2013-10-24
- Earliest claimed: 2012-04-23
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Yoshihiko KAMATA; Yuko YOKOTA; Koji TABATA; Tomoyuki HAMANO; Mario SAKO
- Web page: https://patentgrep.com/patent/US20130279255A1

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/24: Bit-line control circuits
- G11C 16/30: Power supply circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

According to one embodiment, a semiconductor memory device includes a first transistor, a detector, and a second transistor. The first transistor is capable of transferring a first voltage to a bit line. The detector reads data held by a memory cell connected to the bit line. The second transistor is capable of transferring a second voltage and a third voltage to the detector. The second voltage is generated by a source different from a source of the first voltage. The third voltage is larger than the second voltage. The second transistor charges the detector to one of the second voltage and the third voltage, while the first transistor transferring the first voltage to the bit line.

## Claims

### Claim 1

A semiconductor memory device comprising:
a first transistor configured to be capable of transferring a first voltage to a bit line;
a detector configured to read data held by a memory cell connected to the bit line; and
a second transistor configured to be capable of transferring a second voltage and a third voltage to the detector, the second voltage being generated by a source different from a source of the first voltage, the third voltage being larger than the second voltage
wherein the second transistor charges the detector to one of the second voltage and the third voltage, while the first transistor transferring the first voltage to the bit line.

### Claim 2 (depends on 1)

The device according to claim 1, further comprising
a selector configured to output one of the second voltage and the third voltage to the second transistor.

### Claim 3 (depends on 2)

The device according to claim 2, wherein the selector includes a third transistor, the third transistor outputting one of the second voltage and the third voltage to the second transistor, and
the third transistor is an n-channel type MOS transistor.

### Claim 4 (depends on 1)

The device according to claim 1, further comprising:
a third transistor with a current path one end of which is connected to one end of a current path in the first transistor, the third transistor being enable to transfer the voltage of the detector to the bit line; and
a fourth transistor with a current path one end of which is connected to the one end of the current path in the first transistor and to one end of the current path in the third transistor, the fourth transistor clamping the bit line to a fourth voltage,
wherein when the third transistor is turned on, the one end of the current path in the first transistor and the one end of the current path in the fourth transistor are electrically connected to the detector.

### Claim 5 (depends on 1)

The device according to claim 1, further comprising:
a memory cell array including a plurality of NAND strings each comprising a plurality memory cells connected in series;
a voltage generator configured to supply, during reading of the data, a fifth voltage to the source while supplying a sum of a sixth voltage and the fifth voltage to gates of the first transistor and the second transistor;
wherein each of bit lines is connected to the corresponding NAND string, and
a sense amplifier further includes a third transistor, the first transistor and the second transistor, the third transistor and the first transistor connected in series, the first and third transistors charging the bit line to a fifth voltage when the data is to be read from the memory cell.

### Claim 6 (depends on 5)

The device according to claim 5, wherein the voltage generator includes a voltage switching circuit configured to supply the sum of the sixth voltage and the fifth voltage to the first transistor and the third transistor.

### Claim 7 (depends on 6)

The device according to claim 6, wherein
the voltage switching circuit further comprises:
a current source configured to supply a first current to a first node; and
a group of transistors forming a mirror circuit together with the third transistor and passing the first current to a second node,
wherein a number of the transistors in the group forming the mirror circuit corresponds to a channel length between the first transistor and the third transistor,
the voltage switching circuit supplies the gate of the first transistor with a voltage substantially equal to the sum plus a seventh voltage during precharging of the bit line before the data is read.

### Claim 8 (depends on 7)

The device according to claim 7, further comprising:
a controller configured to vary the number of the transistors forming the mirror circuit, and the transistors in the group passing the first current to the second node,
wherein after the precharging and when the data is read, the controller switches the value of the group of the transistors from a first number to a second number smaller than the first number.

### Claim 9 (depends on 8)

The device according to claim 8, wherein the second node includes a third node and a fourth node, and
the group of the transistors forming the mirror circuit includes a first group of transistors passing a current present at the first node to the second node and a second group of transistors passing a current present at the first node to the fourth node, and
the number of the transistors in the group is switched by turning on or off switches connected to the third node and the fourth node, respectively.

### Claim 10 (depends on 1)

The device according to claim 1, further comprising:
a source line driver including a fifth node connected to a source; the source line driver includes a transistor, one end of the current path in the transistor being connected the fifth node and the other end of the current path in the transistor being grounded,
a voltage controller configured to supply a voltage to the fifth node and turn on the transistor to control charge and discharge of the fifth node,
wherein the voltage controller includes:
a voltage booster configured to boost, during a read operation, a voltage of the source via the fifth node, and to detect when the potential of the well is higher than a first value, to stop boosting the potentials of the source and the well; and
a pull-down driver configured to detect the potential of the source and to controllably discharge the potential of the fifth node when the potential of the source exceeds a second value.

### Claim 11 (depends on 10)

The device according to claim 10, further comprising:
a first interconnect configured to connect a sixth node of the source of the first block to the fifth node and having a first length; and
a second interconnect configured to connect a seventh node of the source of the second block to the fifth node and having a second length which is a part of the first interconnect and which is shorter than the first length,
wherein the pull-down driver detects the potential of the sixth node.

### Claim 12 (depends on 11)

The device according to claim 11, wherein the source line driver comprises a first switch configured to discharge the potential of the fifth node, and
the pull-down driver starts discharging the potential of the fifth node via the first switch, while the voltage booster outputting.

### Claim 13 (depends on 11)

The device according to claim 11, further comprising:
a selector comprising a first mode and a second mode and enabling a detection target node to be selected depending on one of the first mode and the second mode,
wherein in the first mode in which the well is charged, the selector makes such a selection as to detect the potential of the well and outputs a result of the detection to the voltage boost section, and
in the second mode in which the well is set to a ground potential and the fifth node is charged, the selector makes such a selection as to detect a potential of the seventh node and outputs a result of the detection to the voltage booster.

### Claim 14 (depends on 10)

The device according to claim 10, further comprising:
bit lines each corresponding to one of the NAND strings and reading the data held by the memory cell;
a driver controllably turning on and off the bit line; and
an accelerator controlling a rising edge of a potential of the bit line,
wherein the accelerator generates a second voltage higher than a first voltage with respect to the potential of the bit line which rises to the first voltage, and outputs the second voltage to the driver.

### Claim 15

A reading method of semiconductor memory device, the method comprising:
transferring a first voltage to a bit line by a first transistor having a first current driving force;
transferring a second voltage to a detector by a second transistor, while the first transistor transfers the first voltage through the bit line, the second voltage being generated by a source different from a source of the first voltage, the detector receiving the second voltage to detect a current flowing through the bit line; and
connecting the detector and the bit line and then transferring read data to a latch circuit depending on the potential of the detector.

### Claim 16 (depends on 15)

The method according to claim 15, further comprising:
selecting the second voltage and outputting the second voltage to the second transistor, by a selector.

### Claim 17 (depends on 16)

The method according to claim 16, further comprising:
stopping the output of the second voltage by the selector when the potential of the detector reaches the second voltage.

### Claim 18

A semiconductor memory device comprising:
a memory cell array comprising a first block and a second block, the first block and the second block each including the plurality of NAND strings each comprising the plurality of memory cells formed on a well and connected in series;
a source line driver setting the well to a ground potential and comprising a first node, the source line driver charging and discharging potentials of the sources of the first block and the second block via the first node; and
a voltage controller configured to supply a voltage to the fifth node and turn on the transistor to control charge and discharge of the first node,
wherein the voltage controller includes:
a voltage booster boosting, during a read operation, a potential of the first node, and upon detecting when the potential of the source of the second block exceeds a predetermined value, stopping boosting the potential of the first node; and
a pull-down driver detecting the potential of the source and to controllably discharge the potential of the first node when the potential of the source exceeds a second predetermined value.

### Claim 19 (depends on 18)

The apparatus according to claim 18, wherein the pull-down driver starts discharging the potential of the first node, while the voltage booster outputting.

### Claim 20 (depends on 18)

The device according to claim 18, further comprising:
bit lines each corresponding to one of the NAND strings and reading the data held by the memory cell;
a driver controllably turning on and off the bit line; and
an accelerator controlling a rising edge of a potential of the bit line,
wherein the accelerator generates a second voltage higher than a first voltage with respect to the potential of the bit line which rises to the first voltage, and supplies the second voltage to the driving circuit.