# US 2013/0278807 A1 · Solid-state imaging device and electronic equipment > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0278807 A1 - Document ID: US20130278807A1 - Status: Published application - Kind: A1 - Application number: 13/920,580 - Filed: 2013-06-18 - Published: 2013-10-24 - Earliest claimed: 2010-10-21 - Assignees: Sony Corporation - Applicants: Sony Corporation - Inventors: Machiko Horiike; Kazuchiro Itonaga - Web page: https://patentgrep.com/patent/US20130278807A1 ## CPC - H10F 39/8023: {Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery} - H04N 25/76: Addressed sensors, e.g. MOS or CMOS sensors - H10F 39/8057: {Optical shielding} - H10F 39/809: {of hybrid image sensors} - H10F 39/811: {Interconnections} - H10F 39/812: {Arrangements for transferring the charges in the image sensor perpendicular to the imaging plane, e.g. buried regions used to transfer generated charges to circuitry under the photosensitive region} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A backside illumination type solid-state imaging device includes stacked semiconductor chips which are formed such that two or more semiconductor chip units are bonded to each other, at least a first semiconductor chip unit is formed with a pixel array and a first multi-layered wiring layer, and a second semiconductor chip unit is formed with a logic circuit and a second multi-layered wiring layer, a connection wire which connects the first semiconductor chip unit and the second semiconductor chip unit, and a first shield wire which shields adjacent connection wires in one direction therebetween. ## Claims ### Claim 1 A backside illumination type solid-state imaging device, comprising: stacked semiconductor chips which are formed such that two or more semiconductor chip units are bonded to each other, at least a first semiconductor chip unit is formed with a pixel array and a first multi-layered wiring layer, and a second semiconductor chip unit is formed with a logic circuit and a second multi-layered wiring layer; a connection wire which connects the first semiconductor chip unit and the second semiconductor chip unit; and a first shield wire which shields adjacent connection wires in one direction therebetween, wherein the connection wire includes a connection conductor which is connected to a first connection pad connected to a necessary first wire in the first multi-layered wiring layer, a penetrating connection conductor which penetrates the first semiconductor chip unit and is connected to a second connection pad connected to a necessary second wire in the second multi-layered wiring layer, and a coupling conductor which couples the connection conductor and the penetrating connection conductor, and wherein the first shield wire is formed with a wiring in a necessary layer in the first multi-layered wiring layer and/or the second multi-layered wiring layer. ### Claim 2 (depends on 1) The solid-state imaging device according to claim 1, further comprising: a second shield wire which shields the connection wire and the first wire and the second wire connected to another connection wire adjacent thereto, wherein the second shield wire is formed with a wiring in a necessary layer in the first multi-layered wiring layer and the second multi-layered wiring layer. ### Claim 3 (depends on 1) The solid-state imaging device according to claim 1, wherein connection wire groups in which the connection wire is arranged in plural in the other direction are arranged in plural in the one direction, and wherein each of the connection wire groups is divided by the continuous first shield wire. ### Claim 4 (depends on 3) The solid-state imaging device according to claim 3, wherein the pixel array includes a photoelectric conversion unit and a plurality of pixels which includes a plurality of pixel transistors and is arrayed in a matrix shape and a vertical signal line commonly connected to pixels in each column, and wherein the vertical signal line corresponds to the first wire. ### Claim 5 (depends on 4) The solid-state imaging device according to claim 4, further comprising: a semiconductor removed area in which the entire semiconductor portion in a part of the first semiconductor chip unit is removed, wherein the connection wire is formed in the semiconductor removed area. ### Claim 6 A backside illumination type solid-state imaging device, comprising: stacked semiconductor chips which are formed such that two or more semiconductor chip units are bonded to each other, at least a first semiconductor chip unit is formed with a pixel array and a first multi-layered wiring layer, and a second semiconductor chip unit is formed with a logic circuit and a second multi-layered wiring layer; a connection wire which connects the first semiconductor chip unit and the second semiconductor chip unit; and a second shield wire which shields the connection wire and a first wire and a second wire which are connected to another connection wire adjacent thereto, wherein the connection wire includes a connection conductor which is connected to a first connection pad connected to a necessary first wire in the first multi-layered wiring layer, a penetrating connection conductor which penetrates the first semiconductor chip unit and is connected to a second connection pad connected to a necessary second wire in the second multi-layered wiring layer, and a coupling conductor which couples the connection conductor and the penetrating connection conductor, and wherein the second shield wire is formed with a wiring in a necessary layer in the first multi-layered wiring layer and the second multi-layered wiring layer. ### Claim 7 (depends on 6) The solid-state imaging device according to claim 6, wherein the pixel array includes a photoelectric conversion unit and a plurality of pixels which includes a plurality of pixel transistors and is arrayed in a matrix shape and a vertical signal line commonly connected to pixels in each column, and wherein the vertical signal line corresponds to the first wire. ### Claim 8 (depends on 7) The solid-state imaging device according to claim 7, further comprising: a semiconductor removed area in which the entire semiconductor portion in a part of the first semiconductor chip unit is removed, wherein the connection wire is formed in the semiconductor removed area. ### Claim 9 Electronic equipment comprising: a solid-state imaging device; an optical system which guides incident light to a photodiode of the solid-state imaging device; and a signal processing circuit which processes output signals of the solid-state imaging device, the solid-state imaging device including stacked semiconductor chips which are formed such that two or more semiconductor chip units are bonded to each other, at least a first semiconductor chip unit is formed with a pixel array and a first multi-layered wiring layer, and a second semiconductor chip unit is formed with a logic circuit and a second multi-layered wiring layer; a connection wire which connects the first semiconductor chip unit and the second semiconductor chip unit; and a first shield wire which shields adjacent connection wires in one direction therebetween, in which the connection wire includes a connection conductor which is connected to a first connection pad connected to a necessary first wire in the first multi-layered wiring layer, a penetrating connection conductor which penetrates the first semiconductor chip unit and is connected to a second connection pad connected to a necessary second wire in the second multi-layered wiring layer, and a coupling conductor which couples the connection conductor and the penetrating connection conductor, and the first shield wire is formed with a wiring in a necessary layer in the first multi-layered wiring layer and/or the second multi-layered wiring layer. ### Claim 10 (depends on 9) The electronic equipment according to claim 9, wherein the solid-state imaging device further includes a second shield wire which shields the connection wire and the first wire and the second wire connected to another connection wire adjacent thereto, in which the second shield wire is formed with a wiring in a necessary layer in the first multi-layered wiring layer and the second multi-layered wiring layer. ### Claim 11 (depends on 9) The electronic equipment according to claim 9, wherein connection wire groups in which the connection wire is arranged in plural in the other direction are arranged in plural in the one direction, and wherein each of the connection wire groups is divided by the continuous first shield wire. ### Claim 12 (depends on 11) The electronic equipment according to claim 11, wherein the pixel array includes a photoelectric conversion unit and a plurality of pixels which includes a plurality of pixel transistors and is arrayed in a matrix shape and a vertical signal line commonly connected to pixels in each column, and wherein the vertical signal line corresponds to the first wire. ### Claim 13 (depends on 12) The electronic equipment according to claim 12, wherein the solid-state imaging device further includes a semiconductor removed area in which the entire semiconductor portion in a part of the first semiconductor chip unit is removed, in which the connection wire is formed in the semiconductor removed area. ### Claim 14 Electronic equipment comprising: a solid-state imaging device; an optical system which guides incident light to a photodiode of the solid-state imaging device; and a signal processing circuit which processes output signals of the solid-state imaging device, the solid-state imaging device including stacked semiconductor chips which are formed such that two or more semiconductor chip units are bonded to each other, at least a first semiconductor chip unit is formed with a pixel array and a first multi-layered wiring layer, and a second semiconductor chip unit is formed with a logic circuit and a second multi-layered wiring layer; a connection wire which connects the first semiconductor chip unit and the second semiconductor chip unit; and a second shield wire which shields the connection wire and a first wire and a second wire which are connected to another connection wire adjacent thereto, in which the connection wire includes a connection conductor which is connected to a first connection pad connected to a necessary first wire in the first multi-layered wiring layer, a penetrating connection conductor which penetrates the first semiconductor chip unit and is connected to a second connection pad connected to a necessary second wire in the second multi-layered wiring layer, and a coupling conductor which couples the connection conductor and the penetrating connection conductor, and the second shield wire is formed with a wiring in a necessary layer in the first multi-layered wiring layer and the second multi-layered wiring layer. ### Claim 15 (depends on 14) The electronic equipment according to claim 14, wherein the pixel array includes a photoelectric conversion unit and a plurality of pixels which includes a plurality of pixel transistors and is arrayed in a matrix shape and a vertical signal line commonly connected to pixels in each column, and wherein the vertical signal line corresponds to the first wire. ### Claim 16 (depends on 15) The electronic equipment according to claim 15, wherein the solid-state imaging device further includes a semiconductor removed area in which the entire semiconductor portion in a part of the first semiconductor chip unit is removed, in which the connection wire is formed in the semiconductor removed area.