# US 2013/0278648 A1 · Display and method for manufacturing display > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0278648 A1 - Document ID: US20130278648A1 - Status: Published application - Kind: A1 - Application number: 13/920,568 - Filed: 2013-06-18 - Published: 2013-10-24 - Earliest claimed: 2006-07-31 - Assignees: Sony Corporation - Applicants: Sony Corporation - Inventors: Tetsuo Minami; Junichi Yamashita; Katsuhide Uchino - Web page: https://patentgrep.com/patent/US20130278648A1 ## CPC - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/30: using electroluminescent panels - G09G 3/3266: Details of drivers for scan electrodes - G09G 5/10: Intensity circuits - H10D 86/0229: {characterised by control of the annealing or irradiation parameters} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - H10H 20/062: {Light-emitting semiconductor devices having field effect type light-emitting regions, e.g. light-emitting High-Electron Mobility Transistors} - G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements - G09G 2300/0417: Special arrangements specific to the use of low carrier mobility technology - G09G 2300/0452: Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0262: The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G 2320/043: Preventing or counteracting the effects of ageing - H10D 62/40: Crystalline structures - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS ## Abstract A display includes a pixel array part with pixels that each have at least one transistor whose conduction state is controlled by a drive signal input to a control terminal, and a scanner including a plurality of buffers that are formed of transistors. The buffers correspond to a pixel arrangement and output a drive signal to the control terminals of the transistors of the pixels. The transistors of the pixels and the transistors of the buffers are formed through irradiation with laser light that is moved for scanning in a predetermined direction and has a predetermined wavelength. The transistors in the buffers are formed in such a way that the channel length direction of the transistors is set parallel to the scan direction of the laser light. ## Claims ### Claim 1 A display comprising: a pixel array part that includes a plurality of pixel circuits that are arranged in a matrix form in columns and rows, each of the plurality of pixel circuits having a pixel transistor whose conduction state is controlled by a drive signal received at a control terminal of the pixel transistor; and a scanner configured to have output stages that are arranged in a column direction and that each are configured to output the drive signal to a corresponding row of the plurality of pixel circuits, wherein each of the output stages includes at least one buffer that comprises buffer transistors that have a channel length extending in the column direction and that are formed through irradiation with laser light. ### Claim 2 (depends on 1) The display of claim 1, wherein a crystal structure of each of the buffer transistors is such that a pitch of crystal grains considered along a center line of the buffer transistor in the row direction is more uniform than a pitch of crystal grains considered along a center line of the buffer transistor in the column direction. ### Claim 3 (depends on 1) The display of claim 1 wherein a crystal structure of each of the buffer transistors is such that crystal grain size considered along a center line of the buffer transistor in the row direction is more uniform than crystal grain size considered along a center line of the buffer transistor in the column direction. ### Claim 4 (depends on 1) The display of claim 1, wherein each of the buffer transistors are arranged in one or more columns in which the buffer transistors thereof are aligned with respect to each other in the column direction. ### Claim 5 (depends on 1) The display of claim 1, wherein, for each of the output stages, the at least one buffer thereof, which includes the buffer transistors, includes a final-stage buffer. ### Claim 6 (depends on 5) The display of claim 5, wherein each of the buffer transistors are arranged in one or more columns in which the buffer transistors thereof are aligned with respect to each other in the column direction. ### Claim 7 (depends on 1) The display of claim 1, wherein, for each of the output stages, the at least one buffer thereof, which includes the buffer transistors, includes an enable pulse buffer that generates an enable pulse of which phase has been corrected. ### Claim 8 (depends on 1) The display of claim 1, wherein the pixel transistor of each of the plurality of pixel circuits is formed through irradiation with laser light and the plurality of pixel circuits are arranged such that each column of the plurality of pixel circuits includes only same-colored pixel circuits. ### Claim 9 (depends on 8) The display of claim 8, wherein a crystal structure of the pixel transistor of each of the plurality of pixel circuits is such that a pitch of crystal grains considered along a center line of the pixel transistor in the row direction is more uniform than a pitch of crystal grains considered along a center line of the pixel transistor in the column direction. ### Claim 10 (depends on 8) The display of claim 8 wherein a crystal structure of the pixel transistor of each of the plurality of pixel circuits is such that crystal grain size considered along a center line of the pixel transistor in the row direction is more uniform than crystal grain size considered along a center line of the pixel transistor in the column direction. ### Claim 11 (depends on 8) The display of claim 8, wherein the pixel transistor of each of the plurality of pixel circuits has a channel length extending in the row direction. ### Claim 12 A display comprising: a pixel array part that includes a plurality of pixel circuits that are arranged in a matrix form in columns and rows, each of the plurality of pixel circuits having a pixel transistor; wherein the respective pixel transistors of the plurality of pixel circuits are formed through irradiation with laser light and have channel lengths extending in the row direction, and the plurality of pixel circuits are arranged in stripes that extend in the column direction, wherein each of the stripes includes only ones of the plurality of pixel circuits of a same color. ### Claim 13 (depends on 13) The display of claim 13, wherein a crystal structure of the pixel transistor of each of the plurality of pixel circuits is such that a pitch of crystal grains considered along a center line of the pixel transistor in the row direction is more uniform than a pitch of crystal grains considered along a center line of the pixel transistor in the column direction. ### Claim 14 (depends on 13) The display of claim 13, wherein a crystal structure of the pixel transistor of each of the plurality of pixel circuits is such that crystal grain size considered along a center line of the pixel transistor in the row direction is more uniform than crystal grain size considered along a center line of the pixel transistor in the column direction. ### Claim 15 A display comprising: a pixel array part that includes a plurality of pixel circuits that are arranged in a matrix form in columns and rows, each of the plurality of pixel circuits having a pixel transistor whose conduction state is controlled by a drive signal received at a control terminal of the pixel transistor; and a scanner configured to have output stages that are arranged in a column direction and that each are configured to output the drive signal to a corresponding row of the plurality of pixel circuits, wherein each of the output stages includes at least one buffer that comprises buffer transistors that have a channel length extending in a first direction and that are formed through irradiation with laser light wherein a crystal structure of each of the buffer transistors is such that a pitch of crystal grains considered along a center line of the buffer transistor in a second direction is more uniform than a pitch of crystal grains considered along a center line of the buffer transistor in the first direction, where the second direction is perpendicular to the first direction.