# US 2013/0278591 A1 · Embedded displayport system and method for controlling panel self refresh mode

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- Number: US 2013/0278591 A1
- Document ID: US20130278591A1
- Status: Published application
- Kind: A1
- Application number: 13/869,619
- Filed: 2013-04-24
- Published: 2013-10-24
- Earliest claimed: 2012-04-24
- Assignees: Silicon Works Co., Ltd.
- Applicants: Silicon Works Co., Ltd.
- Inventors: Yong Hwan MOON; Hong Jun YANG; Sang Ho KIM; Yong Woo KIM
- Web page: https://patentgrep.com/patent/US20130278591A1

## CPC

- G09G 3/3618: {with automatic refresh of the display panel using sense/write circuits}
- G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)}
- G09G 2370/12: Use of DVI or HDMI protocol in interfaces along the display data pipeline
- G09G 2370/14: Use of low voltage differential signaling [LVDS] for display data communication
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

Provided are an embedded DisplayPort (eDP) system and a method for controlling a panel self refresh mode. The eDP system enters a panel self refresh (PSR) mode when an image to display is static in a general mode, and a sink device recovers a stream clock for displaying a static image in the PSR mode.

## Claims

### Claim 1

An embedded DisplayPort (eDP) system comprising:
a source device configured to stop providing a link symbol clock, first stream data having a fixed value, and second stream data having an unfixed value into which variation of the link symbol clock is reflected, when an image to display is static, and enter a panel self refresh (PSR) mode; and
a sink device configured to store a number, obtained by counting an oscillator clock of an embedded oscillator while the link symbol clock is counted by a number corresponding to the first stream data, as first stored stream data, store a number, obtained by counting the stream clock during one period of a divided clock obtained by dividing the oscillator clock by the first stored stream data, as second stored stream data, and recover a stream clock using the oscillator clock and the first and second stored stream data when entering the PSR mode.

### Claim 2 (depends on 1)

The eDP system of claim 1, wherein when the image to display is static, the source device provides a panel mode signal announcing the entry to the PSR mode to the sink device and is then turned off.

### Claim 3 (depends on 1)

The eDP system of claim 1, wherein the sink device comprises:
an oscillator configured to provide the oscillator clock;
a stream data regeneration block configured to output the link symbol clock and the first and second stream data as a reference clock and first and second regenerated stream data in a general mode, and output the oscillator clock and the first and second stored stream data as the reference clock and the first and second regenerated stream data in the PSR mode; and
a stream clock recovery block configured to recover the stream clock using the reference clock and the first and second regenerated stream data.

### Claim 4 (depends on 3)

The eDP system of claim 3, wherein the stream data regeneration block comprises:
a first stored stream data generator configured to generate the first stored stream data based on the number obtained by counting the oscillator clock while the link symbol clock is counted by the number corresponding to the first stream data;
a divider configured to divide the oscillator clock by the first stored stream data;
a second stream data generator configured to generate the second stored stream data based on the number obtained by counting the currently-output stream clock during one period of the divided clock outputted from the divider;
a stream data buffer configured to store the first and second stored stream data and provide the second stored stream data to the divider; and
a selection circuit configured to select and output the link symbol clock and the first and second stream data as the reference clock and the first and second regenerated stream data in the general mode, and select and output the oscillator clock and the first and second stored stream data stored in the stream data buffer as the reference clock and the first and second regenerated stream data according to the panel mode signal in the PSR mode.

### Claim 5 (depends on 4)

The eDP system of claim 4, wherein the first stored stream data generator generates the value of the first stored stream data based on the relation between the link symbol clock and the oscillator clock, which is defined as follows:
f_OSC

_CLK
=
N
*
N
×
f_LS

_CLK
and
N
f_LS

_CLK
=
N
*
f_OSC

_CLK
,
where f_OSC_CLK represents the frequency of the oscillator clock, f_LS_CLK represents the frequency of the link symbol clock, N represents the first stream data, and N* represents the first stored stream data.

### Claim 6 (depends on 4)

The eDP system of claim 4, wherein the second stored stream data generator generates the value of the second stored stream data based on the relation between the link symbol clock and the oscillator clock, which is defined as follows:
f_STR

_CLK
=
M
*
N
*
×
f_OSC

_CLK
and
M
*
f_STR

_CLK
=
N
*
f_OSC

_CLK
=
1
f_D

_CLK
,
where f_STR_CLK represents the frequency of the stream clock, f_OSC_CLK represents the frequency of the oscillator clock, N* represents the first stored stream data, and M* represents the second stored stream data.

### Claim 7 (depends on 3)

The eDP system of claim 3, wherein the stream clock recovery block comprises:
a first divider configured to generate a reference pulse by dividing the reference clock by the first regenerated stream data;
a second divider configured to generate a feedback pulse by dividing the stream clock by the second regenerated stream data; and
a stream clock recovery circuit configured to compare the reference pulse of the first divider to the feedback pulse of the second divider and recover and output the stream clock.

### Claim 8 (depends on 3)

The eDP system of claim 3, wherein the stream clock recovery block recovers the stream clock in the PSR mode based on the relation between the stream clock and the oscillator clock, which is defined as follows:
f_STR

_CLK
=
M
*
N
*
×
f_OSC

_CLK
,
where f_STR_CLK represents the frequency of the stream clock, N* represents the first stored stream data, M* represents the second stored stream data, and f_OSC_CLK represents the frequency of the oscillator clock.

### Claim 9

An eDP system comprising a timing controller configured to recover a stream clock,
wherein the timing controller comprises:
an oscillator configured to provide an oscillator clock;
a stream data regeneration block configured to output a link symbol clock and first and second stream data, transmitted from a source device, as a reference clock and first and second regenerated stream data in a general mode, store a number, obtained by counting the oscillator clock while the link symbol clock is counted by a number corresponding to the first stream data, as first stored stream data, store a number, obtained by counting the stream clock during one period of a divided clock obtained by dividing the oscillator clock by the first stored stream data, as second stored stream data, and output the oscillator clock and the first and second stored stream data as the reference clock and the first and second regenerated stream data according to a panel mode signal in a PSR mode; and
a stream clock recovery block configured to recover the stream clock using the reference clock and the first and second regenerated stream data.

### Claim 10 (depends on 9)

The eDP system of claim 9, wherein the stream data regeneration block comprises:
a first stored stream data generator configured to generate the first stored stream data based on the number obtained by counting the oscillator clock while the link symbol clock is counted by the number corresponding to the first stream data;
a divider configured to divide the oscillator clock by the first stored stream data;
a second stream data generator configured to generate the second stored stream data based on the number obtained by counting the currently-output stream clock during one period of a divided clock outputted from the divider;
a stream data buffer configured to store the first and second stored stream data and provide the second stored stream data to the divider; and
a selection circuit configured to select and output the link symbol clock and the first and second stream data as the reference clock and the first and second regenerated stream data in the general mode, and select and output the oscillator clock and the first and second stored stream data stored in the stream data buffer as the reference clock and the first and second regenerated stream data according to the panel mode signal in the PSR mode.

### Claim 11 (depends on 10)

The eDP system of claim 10, wherein the first stored stream data generator generates the value of the first stored stream data based on the relation between the link symbol clock and the oscillator clock, which is defined as follows:
f_OSC

_CLK
=
N
*
N
×
f_LS

_CLK
and
N
f_LS

_CLK
=
N
*
f_OSC

_CLK
,
where f_OSC_CLK represents the frequency of the oscillator clock, f_LS_CLK represents the frequency of the link symbol clock, N represents the first stream data, and N* represents the first stored stream data.

### Claim 12 (depends on 10)

The eDP system of claim 10, wherein the second stored stream data generator generates the value of the second stored stream data based on the relation between the link symbol clock and the oscillator clock, which is defined as follows:
f_STR

_CLK
=
M
*
N
*
×
f_OSC

_CLK
and
M
*
f_STR

_CLK
=
N
*
f_OSC

_CLK
=
1
f_D

_CLK
,
where f_STR_CLK represents the frequency of the stream clock, f_OSC_CLK represents the frequency of the oscillator clock, N* represents the first stored stream data, and M* represents the second stored stream data.

### Claim 13 (depends on 9)

The eDP system of claim 9, wherein the stream clock recovery block comprises:
a first divider configured to generate a reference pulse by dividing the reference clock by the first regenerated stream data;
a second divider configured to generate a feedback pulse by dividing the stream clock by the second regenerated stream data; and
a stream clock recovery circuit configured to compare the reference pulse of the first divider to the feedback pulse of the second divider and recover and output the stream clock.

### Claim 14 (depends on 9)

The eDP system of claim 9, wherein the stream clock recovery block recovers the stream clock in the PSR mode based on the relation between the stream clock and the oscillator clock, which is defined as follows:
f_STR

_CLK
=
M
*
N
*
×
f_OSC

_CLK
,
where f_STR_CLK represents the frequency of the stream clock, N* represents the first stored stream data, M* represents the second stored stream data, and f_OSC_CLK represents the frequency of the oscillator clock.

### Claim 15

An eDP system comprising a timing controller configured to generate a reference clock for recovering a stream clock,
wherein the timing controller comprises:
an oscillator configured to provide an oscillator clock;
a first stored stream data generator configured to generate first stored stream data based on a number obtained by counting the oscillator clock while a link symbol clock transmitted from a source device is counted by a number corresponding to first stream data transmitted from the source device;
a divider configured to divide the oscillator clock by the first stored stream data;
a second stored stream data generator configured to generate second stored stream data based on a number obtained by counting a currently-output stream clock during one period of a divided clock outputted from the divider;
a stream data buffer configured to store the first and second stored stream data and provide the second stored stream data to the divider; and
a selection circuit configured to select and output the link symbol clock and the first and second stream data as the reference clock and first and second regenerated stream data in a general mode and select and output the oscillator clock and the first and second stored stream data stored in the stream data buffer as the reference clock and the first and second regenerated stream data in response to a panel mode signal in a PSR mode.

### Claim 16 (depends on 15)

The eDP system of claim 15, wherein the first stored stream data generator generates the value of the first stored stream data based on the relation between the link symbol clock and the oscillator clock, which is defined as follows:
f_OSC

_CLK
=
N
*
N
×
f_LS

_CLK
and
N
f_LS

_CLK
=
N
*
f_OSC

_CLK
,
where f_OSC_CLK represents the frequency of the oscillator clock, f_LS_CLK represents the frequency of the link symbol clock, N represents the first stream data, and N* represents the first stored stream data.

### Claim 17 (depends on 15)

The eDP system of claim 15, wherein the second stored stream data generator generates the value of the second stored stream data based on the relation between the link symbol clock and the oscillator clock, which is defined as follows:
f_STR

_CLK
=
M
*
N
*
×
f_OSC

_CLK
and
M
*
f_STR

_CLK
=
N
*
f_OSC

_CLK
=
1
f_D

_CLK
,
where f_STR_CLK represents the frequency of the stream clock, f_OSC_CLK represents the frequency of the oscillator clock, N* represents the first stored stream data, and M* represents the second stored stream data.

### Claim 18

A method for controlling a PSR mode of an eDP system, comprising:
storing a number, obtained by counting an oscillator clock provided from an oscillator while a link symbol clock is counted by a number corresponding to first stream data having a fixed value, as first stored stream data in a general mode;
storing a number, obtained by counting a stream clock during one period of a divided clock obtained by dividing the oscillator clock by the first stored stream data, as second stored stream data in the general mode; and
selecting the oscillator clock and the first and second stored stream data and providing the selected clock and data as a reference clock and first and second regenerated stream data for recovering a stream clock in a PSR mode.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first stored stream data is generated based on the relation between the link symbol clock and the oscillator clock, which is defined as follows:
f_OSC

_CLK
=
N
*
N
×
f_LS

_CLK
and
N
f_LS

_CLK
=
N
*
f_OSC

_CLK
,
where f_OSC_CLK represents the frequency of the oscillator clock, f_LS_CLK represents the frequency of the link symbol clock, N represents the first stream data, and N* represents the first stored stream data.

### Claim 20 (depends on 18)

The method of claim 18, wherein the second stored stream data is generated based on the relation between the link symbol clock and the oscillator clock, which is defined as follows:
f_STR

_CLK
=
M
*
N
*
×
f_OSC

_CLK
and
M
*
f_STR

_CLK
=
N
*
f_OSC

_CLK
=
1
f_D

_CLK
,
where f_STR_CLK represents the frequency of the stream clock, f_OSC_CLK represents the frequency of the oscillator clock, N* represents the first stored stream data, and M* represents the second stored stream data.