# US 2013/0278584 A1 · Driving circuit of display panel capable of eliminating flash

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- Number: US 2013/0278584 A1
- Document ID: US20130278584A1
- Status: Published application
- Kind: A1
- Application number: 13/687,129
- Filed: 2012-11-28
- Published: 2013-10-24
- Earliest claimed: 2012-04-23
- Assignees: Sitronix Technology Corp.
- Applicants: Sitronix Technology Corp.
- Inventors: MIN-NAN LIAO
- Web page: https://patentgrep.com/patent/US20130278584A1

## CPC

- G06F 3/038: Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry
- G09G 3/3685: {Details of drivers for data electrodes}
- G09G 3/3688: {suitable for active matrices only}
- G09G 3/3696: {Generation of voltages supplied to electrode drivers}
- G09G 2320/0276: for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present invention relates to a driving circuit of display panel capable of eliminating flash, which comprises a scan driving circuit and a data driving circuit. The scan driving circuit produces a plurality of scan signals for scanning a plurality of pixel structures of the display panel. The data driving circuit produces a plurality of data signals for transmitting the plurality of data signals to the plurality of pixel structures when the plurality of pixel structures are scanned. When the data driving circuit transmits the plurality of data signals to the plurality of pixel structures, the data driving circuit adjusts the voltage levels of the data signals of the plurality of pixel structures to be symmetrical to a common voltage of the plurality of pixel structures.

## Claims

### Claim 1

A driving circuit of display panel capable eliminating flash, comprising:
a scan driving circuit, producing a plurality of scan signals, and scanning a plurality of pixel structures of said display panel; and
a data driving circuit, producing a plurality of data signals, and transmitting said plurality of data signals to said plurality of pixel structures when said plurality of pixels structures are scanned; where when said data driving circuit transmits said plurality of data signals to said plurality of adjacent pixel structures, said data driving circuit adjusts the voltage levels of said data signals of said plurality of adjacent pixel structures to be symmetrical to a common voltage of said plurality of pixel structures.

### Claim 2 (depends on 1)

The driving circuit of claim 1, wherein said data driving circuit comprises:
a compensation circuit, producing a compensation signal;
a gamma voltage generating circuit, generating a plurality of gamma voltages according to said compensation signal and gamma curve data; and
a plurality of digital-to-analog converters, selecting a portion of said plurality of gamma voltages according to a plurality of display signals for outputting and driving said display panel;
where said compensation signal of said compensation circuit adjusts the signal levels of said plurality of gamma voltages for adjusting the voltage levels of said data signals of said plurality of adjacent pixel structures to be symmetrical to said common voltage of said plurality of pixel structures.

### Claim 3 (depends on 2)

The driving circuit of claim 2, wherein said data driving circuit further comprises a plurality of buffer units, corresponding to said plurality of digital-to-analog converters, producing a plurality of data signals according to said plurality of gamma voltages output by said plurality of digital-to-analog converters for driving said display panel.

### Claim 4 (depends on 2)

The driving circuit of claim 2, wherein said gamma voltage generating circuit comprises:
a voltage dividing circuit, producing a plurality of voltage dividing signals; and
a gamma voltage selecting unit, coupled to said voltage dividing unit, and selecting a portion of said plurality of voltage dividing signals according to said gamma curve data for producing said plurality of gamma voltages.

### Claim 5 (depends on 2)

The driving circuit of claim 2, and further comprising:
an input/output interface, receiving said gamma curve data and said display signal; and
a gamma curve data register, coupled to said input/output interface, registering said gamma curve data, and transmitting said gamma curve data to said gamma voltage generating circuit.

### Claim 6 (depends on 5)

The driving circuit of claim 5, and further comprising:
a display memory, coupled to said input/output interface, and storing said display signal;
a shift register, coupled to said display memory, and receiving and shifting said display signal; and
a buffer circuit, coupled to said shift register, buffering and transmitting said display signal to said plurality of digital-to-analog converters.

### Claim 7 (depends on 4)

The driving circuit of claim 4, wherein said compensation circuit comprises:
a compensation unit, producing a compensation signal;
an adjusting circuit, receiving a power supply voltage, and dividing said power supply voltage for producing a plurality of adjusting signals; and
a switching circuit, coupled to said adjusting circuit, selecting said plurality of adjusting signals for producing a first reference voltage and a second reference voltage, and transmitting said first reference voltage and said second reference voltage to said voltage dividing circuit so that said voltage dividing circuit producing said plurality of voltage dividing signals according to said first reference voltage and said second reference voltage.

### Claim 8 (depends on 7)

The driving circuit of claim 7, wherein said gamma voltage generating circuit further comprises:
a first amplifying unit, coupled to said switching circuit, and buffering and transmitting said first reference voltage to said voltage dividing circuit; and
a second amplifying unit, coupled to said switching circuit, and buffering and transmitting said second reference voltage to said voltage dividing circuit.

### Claim 9 (depends on 2)

The driving circuit of claim 2, and further comprising an operational circuit, calculating said gamma curve data and said compensation signal for producing an operational signal, and transmitting said operational signal to said gamma voltage generating circuit for generating said plurality of gamma voltages.