# US 2013/0278487 A1 · Layout structure and pixel structure of display panel

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- Number: US 2013/0278487 A1
- Document ID: US20130278487A1
- Status: Published application
- Kind: A1
- Application number: 13/522,702
- Filed: 2012-04-23
- Published: 2013-10-24
- Earliest claimed: 2012-04-19
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Hung-Lung Hou
- Web page: https://patentgrep.com/patent/US20130278487A1

## CPC

- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G09G 3/18: using liquid crystals
- G02F 1/1362: Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/13456: {Cell terminals located on one side of the display only}
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G09G 2300/0426: Layout of electrodes and connections
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A layout structure of a display panel is disclosed. The layout structure comprises: a plurality of gate lines; a plurality of source lines which are interlaced with the gate lines to construct a plurality of pixel units; and a plurality of connecting lines which are electrically connected to the gate lines or the source lines in a one-to-one relationship and are extended to the same side or two corresponding sides of the display panel. The present invention can reduce the layout area of the source driver and the gate driver. It is quite beneficial to the development on narrow-border display products.

## Claims

### Claim 1

A layout structure of a display panel, comprising:
a plurality of gate lines;
a plurality of source lines, which are interlaced with the gate lines to construct a plurality of pixel units; and
a plurality of source connecting lines, which are parallel to the gate lines, wherein corresponding ends of the source connecting lines are electrically connected to the source lines in a one-to-one relationship via a plurality of connecting points, respectively.

### Claim 2 (depends on 1)

The layout structure according to claim 1, wherein the display panel comprises a source driver, another set of corresponding ends of the source connecting lines is electrically connected to an output terminal of the source driver for receiving data signals outputted from the source driver.

### Claim 3 (depends on 2)

The layout structure according to claim 2, wherein the display panel comprises a first metal layer, a second metal layer, and an insulating layer located between the first metal layer and the second metal layer, wherein the gate lines are formed in the first metal layer, the source lines are formed in the second metal layer, and the source connecting lines are formed in the first metal layer and are electrically connected to the source lines formed in the second metal layer via contact holes.

### Claim 4 (depends on 3)

The layout structure according to claim 3, further comprising a plurality of common lines, which are formed in the second metal layers and are parallel to the source lines, wherein the common lines have shield structures disposed corresponding to a region where the source connecting lines pass by.

### Claim 5

A layout structure of a display panel, comprising:
a plurality of gate lines;
a plurality of source lines, which are interlaced with the gate lines to construct a plurality of pixel units; and
a plurality of connecting lines, which are electrically connected to the gate lines or the source lines in a one-to-one relationship and are extended to the same side or two corresponding sides of the display panel.

### Claim 6 (depends on 5)

The layout structure according to claim 5, wherein the connecting lines are source connecting lines which are parallel to the gate lines, corresponding ends of the source connecting lines are electrically connected to the source lines via a plurality of connecting points, respectively.

### Claim 7 (depends on 6)

The layout structure according to claim 6, wherein the display panel comprises a source driver, another set of corresponding ends of the source connecting lines are electrically connected to an output terminal of the source driver for receiving data signals outputted from the source driver.

### Claim 8 (depends on 6)

The layout structure according to claim 6, wherein the display panel comprises a first metal layer, a second metal layer, and an insulating layer located between the first metal layer and the second metal layer, wherein the gate lines are formed in the first metal layer, the source lines are formed in the second metal layer, and the source connecting lines are formed in the first metal layer and are electrically connected to the source lines formed in the second metal layer via contact holes.

### Claim 9 (depends on 8)

The layout structure according to claim 8, further comprising a plurality of common lines, which are formed in the second metal layers and are parallel to the source lines, wherein the common lines have shield structures disposed corresponding to a region where the source connecting lines pass by.

### Claim 10 (depends on 5)

The layout structure according to claim 5, wherein the connecting lines are gate connecting lines which are parallel to the source lines, corresponding ends of the gate connecting lines are electrically connected to the gate lines via a plurality of connecting points, respectively.

### Claim 11 (depends on 10)

The layout structure according to claim 10, wherein the display panel comprises a gate driver, another set of corresponding ends of the gate connecting lines is electrically connected to an output terminal of the gate driver for receiving scan signals outputted from the gate driver.

### Claim 12 (depends on 10)

The layout structure according to claim 10, wherein the display panel comprises a first metal layer, a second metal layer, and an insulating layer located between the first metal layer and the second metal layer, wherein the gate lines are formed in the first metal layer, the source lines are formed in the second metal layer, and the gate connecting lines are formed in the second metal layer and are electrically connected to the gate lines formed in the first metal layer via contact holes.

### Claim 13

A pixel structure of a display panel, having a transistor, in which the pixel structure is constructed by interlacing two gate lines with two source lines, one gate line that corresponds to the pixel structure transmits a scan signal for turning on the transistor of the pixel structure, and one data line that corresponds to the pixel structure transmits a data signal to the pixel structure when the transistor is turned on, wherein the pixel structure comprises:
a connecting line which is electrically connected to the gate line corresponding to the pixel structure or the source line corresponding to the pixel structure, and is extended to an external portion.

### Claim 14 (depends on 13)

The pixel structure according to claim 13, wherein the connecting line is a source connecting line which is parallel to the two gate lines, the source connecting line is electrically connected to the source line that corresponds to the pixel structure via a connecting point.

### Claim 15 (depends on 13)

The pixel structure according to claim 13, wherein the connecting line is a gate connecting line which is parallel to the two source lines, the gate connecting line is electrically connected to the gate line that corresponds to the pixel structure via a connecting point.
