# US 2013/0278452 A1 · System and method of clocking low sample rate analog to digital converters while minimizing linearity errors

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0278452 A1
- Document ID: US20130278452A1
- Status: Published application
- Kind: A1
- Application number: 13/451,774
- Filed: 2012-04-20
- Published: 2013-10-24
- Earliest claimed: 2012-04-20
- Assignees: Texas Instruments Incorporated
- Inventors: Haydar Bilhan; Maher Mahmoud Sarraj
- Web page: https://patentgrep.com/patent/US20130278452A1

## CPC

- H03M 1/466: {using switched capacitors}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.

## Claims

### Claim 1

A successive approximation register analog to digital converter comprising:
(a) a switched capacitor digital to analog converter having an output;
(b) a comparator having an input sense node coupled to the output of the switched capacitor digital to analog converter;
(c) at least one reset switch coupled between the input sense node on the comparator and a reference voltage; and,
(d) a clocking system to provide timing to operate at lower sample rates wherein successive approximation cycles are clocked at the same clock pulse irrespective of the sample rate but wherein an end of conversion signal is delayed to mimic a slower sample rate.

### Claim 2 (depends on 1)

A successive approximation register analog to digital converter of claim 1 further comprising a programmable register for programming sample rate reduction ratio.

### Claim 3 (depends on 1)

A successive approximation register analog to digital converter of claim 1 wherein at least two reset switches are used for reading a differential voltage input to the comparator.

### Claim 4 (depends on 1)

A successive approximation register analog to digital converter of claim 1 wherein the reference voltage is substantially one half of supply voltage.

### Claim 5

An analog to digital converter comprising:
(a) a switched capacitor digital to analog converter having an output;
(b) a comparator having an input sense node;
(c) at least one reset switch coupled between the input sense node on the comparator and a reference voltage; and
(d) a clocking system having an end of conversion generator and a timing generator both having a first input coupled to a start of conversion signal, the end of conversion generator having a second input coupled to a system clock and an output, a clock multiplier having an input coupled to the system clock and an output coupled to a second input on the timing generator.

### Claim 6 (depends on 5)

An analog to digital converter of claim 5 wherein the clock multiplier is a phase locked loop with a programmable register to adjust a multiplying factor N.

### Claim 7 (depends on 5)

An analog to digital converter of claim 5 wherein at least two reset switches are used for reading a differential voltage input to input sense nodes to the comparator

### Claim 8 (depends on 5)

An analog to digital converter of claim 5 wherein the reference voltage is substantially one half of supply voltage.

### Claim 9

A method of successive approximation conversion in an analog to digital converter having a comparator, at least one reset switch coupled to an input sense node on the comparator and a switched capacitor DAC, comprising steps of:
(a) coupling the input sense node of the comparator to a reference voltage during periods of non-conversion;
(b) using a constant clock frequency for switching the switched capacitor DAC and at the least one reset switch; and,
(c) delaying issuance of an end of conversion signal to mimic a slower sample rate.

### Claim 10 (depends on 9)

A method of claim 9 further comprising the step of multiplying a system clock by a multiplier N to produce the constant clock frequency.

### Claim 11 (depends on 10)

A method of claim 10 wherein the step of multiplying further includes the step of programming a register with the multiplier N.

### Claim 12 (depends on 9)

A method of claim 9 wherein at least two reset switches are used for reading a differential voltage input to the comparator.

### Claim 13 (depends on 9)

A method of claim 9 wherein the reference voltage is substantially one half of supply voltage.