# US 2013/0278451 A1 · Binary-to-Gray Converting Circuits and Gray Code Counter Including the Same

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- Number: US 2013/0278451 A1
- Document ID: US20130278451A1
- Status: Published application
- Kind: A1
- Application number: 13/764,262
- Filed: 2013-02-11
- Published: 2013-10-24
- Earliest claimed: 2012-04-24
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Kyung-Min Kim; Jin-Woo Kim; Hee-Sung Chae
- Web page: https://patentgrep.com/patent/US20130278451A1

## CPC

- H03M 7/16: Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
- H03K 23/005: {using minimum change code, e.g. Gray Code}
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

A binary-to-Gray converting circuit includes a buffer unit and a conversion unit. The buffer unit generates a data code of n bits in response to a power supply voltage and a second binary bit signal through an nth binary bit signal except for a first binary bit signal corresponding to a least significant bit of a binary code of n bits. The conversion unit generates a Gray code of n bits based on the binary code and the data code, and generates a kth Gray bit signal of the Gray code by latching a kth data bit signal of the data code in response to a kth binary bit signal of the binary code. A logic level of the kth Gray bit signal is determined corresponding to a logic level of the kth data bit signal.

## Claims

### Claim 1

A binary-to-Gray converting circuit, comprising:
a buffer unit configured to generate a data code of n bits, where n is a natural number equal to or greater than two, in response to a power supply voltage and a second binary bit signal through an nth binary bit signal except for a first binary bit signal, the first binary bit signal corresponding to a least significant bit of a binary code of n bits, the second through nth binary bit signals corresponding to other bits of the binary code; and
a conversion unit configured to generate a Gray code of n bits based on the binary code and the data code, and configured to generate a kth Gray bit signal, where k is a natural number equal to or greater than one and equal to or less than n, by latching a kth data bit signal in response to a kth binary bit signal, a logic level of the kth Gray bit signal being determined corresponding to a logic level of the kth data bit signal, the kth Gray bit signal corresponding to a kth bit of the Gray code, the kth data bit signal corresponding to a kth bit of the data code, and the kth binary bit signal corresponding to a kth bit of the binary code.

### Claim 2 (depends on 1)

The binary-to-Gray converting circuit of claim 1, wherein the conversion unit includes a first flip-flop through an nth flip-flop, each of the first through nth flip-flops generates one of a first Gray bit signal through an nth Gray bit signal corresponding to a respective one of a first bit through an nth bit of the Gray code.

### Claim 3 (depends on 2)

The binary-to-Gray converting circuit of claim 2, wherein each of the first through nth flip-flops includes:
a data input terminal configured to receive one of a first data bit signal through an nth data bit signal corresponding to a respective one of a first bit through an nth bit of the data code;
a clock input terminal configured to receive a respective one of the first through nth binary bit signals; and
a data output terminal configured to output a respective one of the first through nth Gray bit signals.

### Claim 4 (depends on 3)

The binary-to-Gray converting circuit of claim 3, wherein the buffer unit includes a first inverter through an (n-1)th inverter, each of the first through (n-1)th inverters generates a respective one of the first through (n-1)th data bit signals.

### Claim 5 (depends on 4)

The binary-to-Gray converting circuit of claim 4, wherein an mth inverter, where m is a natural number equal to or greater than one and equal to or less than (n-1), inverts an (m+1)th binary bit signal to generate an mth data bit signal.

### Claim 6 (depends on 5)

The binary-to-Gray converting circuit of claim 5, wherein the buffer unit outputs the power supply voltage as the nth data bit signal.

### Claim 7 (depends on 6)

The binary-to-Gray converting circuit of claim 6, wherein each of the first through nth flip-flops is a positive-edge triggered D flip-flop operating in response to a rising edge of the respective one of the first through nth binary bit signals.

### Claim 8 (depends on 2)

The binary-to-Gray converting circuit of claim 2, wherein each of the first through nth flip-flops includes:
a data input terminal configured to receive one of a first data bit signal through an nth data bit signal corresponding to a respective one of a first bit through an nth bit of the data code;
a clock input terminal configured to receive an inversion signal of a respective one of the first through nth binary bit signals; and
an inverted-data output terminal configured to output a respective one of the first through nth Gray bit signals.

### Claim 9 (depends on 8)

The binary-to-Gray converting circuit of claim 8, wherein the buffer unit includes a first inverter through an (n-1)th inverter, each of the first through (n-1)th inverters generates a respective one of the first through (n-1)th data bit signals,
wherein an mth inverter, where m is a natural number equal to or greater than one and equal to or less than (n-1), inverts an (m+1)th binary bit signal to generate an mth data bit, and the buffer unit outputs the power supply voltage as the nth data bit signal.

### Claim 10 (depends on 9)

The binary-to-Gray converting circuit of claim 9, wherein each of the first through nth flip-flops is a negative-edge triggered D flip-flop operating in response to a falling edge of the respective one of the first through nth binary bit signals.

### Claim 11

A Gray code counter, comprising:
a binary counter circuit configured to generate a binary code of n bits, where n is a natural number equal to or greater than two, based on a power supply voltage and a clock signal; and
a binary-to-Gray converting circuit configured to generate a Gray code of n bits based on the binary code and the power supply voltage,
wherein the binary-to-Gray converting circuit comprises:
a buffer unit configured to generate a data code of n bits in response to the power supply voltage and a second binary bit signal to an nth binary bit signal except for a first binary bit signal, the first binary bit signal corresponding to a least significant bit of the binary code, the second through nth binary bit signals corresponding to other bits of the binary code, the first through nth binary bit signals being sequentially toggled; and
a conversion unit configured to generate the Gray code based on the binary code and the data code, and configured to generate a kth Gray bit signal, where k is a natural number equal to or greater than one and equal to or less than n, by latching a kth data bit signal in response to a kth binary bit signal of the binary code, a logic level of the kth Gray bit signal being determined corresponding to a logic level of the kth data bit signal, the kth Gray bit signal corresponding to a kth bit of the Gray code, the kth data bit signal corresponding to a kth bit of the data code, and the kth binary bit signal corresponding to a kth bit of the binary code.

### Claim 12 (depends on 11)

The Gray code counter of claim 11, wherein the binary counter circuit is a synchronous counter circuit or an asynchronous counter circuit.

### Claim 13 (depends on 12)

The Gray code counter of claim 12, wherein the binary counter circuit includes a first flip-flop through an nth flip-flop that are cascade-connected, each of the first through nth flip-flops generate one of the first through nth binary bit signals in response to the clock signal.

### Claim 14 (depends on 11)

The Gray code counter of claim 11, wherein the binary counter circuit performs an up-counting operation or a down-counting operation.

### Claim 15 (depends on 14)

The Gray code counter of claim 14, wherein the conversion unit includes a first flip-flop through an nth flip-flop, each of the first through nth flip-flops generate one of a first Gray bit signal through an nth Gray bit signal corresponding to a respective one of a first bit through an nth bit of the Gray code, and
wherein each of the first through nth flip-flops is a positive-edge triggered D flip-flop operating in response to a rising edge of a respective one of the first through nth binary bit signals when the binary counter circuit performs the up-countering operation, and is a negative-edge triggered D flip-flop operating in response to a falling edge of a respective one of the first through nth binary bit signals when the binary counter circuit performs the down-countering operation.

### Claim 16

A binary-to-Gray converting circuit, comprising:
a buffer unit configured output a clock signal and a data signal, both based on a bit included in a binary code to be translated to a Gray code by the binary-to-Gray converting circuit; and
a conversion unit, coupled to the buffer unit, configured to receive the clock signal at a clock input terminal of an upper stage of the conversion unit and configured to receive the data signal at a data input terminal of a lower stage of the conversion unit, relative to the upper stage.

### Claim 17 (depends on 16)

The circuit of claim 16 wherein the buffer unit further comprises:
an input terminal configured to receive the bit included in the binary code to be translated to a Gray code;
an output terminal, coupled to the input terminal, configured to provide the bit to the clock input terminal of the upper stage of the conversion unit as the clock signal; and
an inverter circuit, coupled to the input terminal, configured to invert the bit to provide the data signal to the lower stage of the conversion unit.

### Claim 18 (depends on 16)

The circuit of claim 16 wherein the buffer unit is configured to receive a plurality of parallel bits included in the binary code and is configured to provide a respective plurality of parallel bits included in a data code provided to the conversion unit; and
the conversion unit is configured to receive the respective plurality of parallel bits included in a data code at respective stages of the conversion unit .

### Claim 19 (depends on 18)

The circuit of claim 18 wherein an uppermost stage of the conversion unit receives a static power supply voltage signal as an uppermost bit included in the data code.

### Claim 20 (depends on 18)

The circuit of claim 18 wherein a lower order bit included in the binary code is provided as a lowest stage clock input to the conversion unit.

### Claim at position 21

-23. (canceled)