# US 2013/0278348 A1 · Crosstalk cancellation and/or reduction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0278348 A1 - Document ID: US20130278348A1 - Status: Published application - Kind: A1 - Application number: 13/976,780 - Filed: 2011-12-19 - Published: 2013-10-24 - Earliest claimed: 2011-12-19 - Assignees: Intel Corporation - Inventors: Xiaoning Ye - Web page: https://patentgrep.com/patent/US20130278348A1 ## CPC - H01P 1/227: {Strip line attenuators (H01P1/23 takes precedence)} - H01R 13/6471: by special arrangement of ground and signal conductors, e.g. GSGS [Ground-Signal-Ground-Signal] - H04L 25/03878: {Line equalisers; line build-out devices} - H05K 1/0228: {Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors (balanced signal pairs H05K1/0245)} - H05K 1/0245: {Lay-out of balanced signal pairs, e.g. differential lines or twisted lines} - H01P 3/026: {Coplanar striplines [CPS]} - H05K 2201/09236: Parallel layout - H05K 2201/10189: Non-printed connector - H01P: WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE (operating at optical frequencies G02B) - H01R: ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract Some embodiments include a first differential signal pair and a second differential signal pair. The first and second differential signal pairs are arranged relative to each other in a manner to intentionally reduce or cancel crosstalk introduced by a pinout (for example, a section of a pinout, a socket, a connector, etc.) into at least one of the first differential signal pair and the second differential signal pair. Other embodiments are described and claimed. ## Claims ### Claim 1 An apparatus comprising: a first differential signal pair; and a second differential signal pair; wherein the first and second differential signal pair are arranged relative to each other in a manner to intentionally reduce or cancel crosstalk introduced by a pinout into at least one of the first differential signal pair and the second differential signal pair. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising microstrip routing of the first differential signal pair and/or the second differential signal pair in an area near the pinout to reduce or cancel the crosstalk introduced by the pinout. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the microstrip routing of the first differential signal pair and/or the second differential signal pair is just before or just after the pinout. ### Claim 4 (depends on 1) The apparatus of claim 1, further comprising routing near each other the first differential signal pair and/or the second differential signal pair in an area near the pinout. ### Claim 5 (depends on 1) The apparatus of claim 1, further comprising microstrip routing near each other the first differential signal pair and/or the second differential signal pair in an area near the pinout. ### Claim 6 (depends on 1) The apparatus of claim 1, further comprising routing in an area near the pinout a negative polarity signal of the first differential pair and a negative polarity signal of the second differential pair nearer to each other than any other signals of the first differential pair and the second differential pair. ### Claim 7 (depends on 1) The apparatus of claim 1, further comprising routing in an area near the pinout a positive polarity signal of the first differential pair and a positive polarity signal of the second differential pair nearer to each other than any other signals of the first differential pair and the second differential pair. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the first differential signal pair and the second differential signal pair comprise high speed serial links. ### Claim 9 (depends on 1) The apparatus of claim 1, further comprising in an area near the pinout reversing a position of a negative and positive polarity signals of one of the first differential signal pair and the second differential signal pair. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein in an area near the pinout the negative polarity signal of the first differential signal pair is closer to the second differential signal pair than the positive polarity signal of the first differential signal pair, and wherein the negative polarity signal of the second differential signal pair is closer to the first differential signal pair than the positive polarity signal of the second differential signal pair. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein in an area near the pinout the positive polarity signal of the first differential signal pair is closer to the second differential signal pair than the negative polarity signal of the first differential signal pair, and wherein the positive polarity signal of the second differential signal pair is closer to the first differential signal pair than the negative polarity signal of the second differential signal pair. ### Claim 12 (depends on 1) The apparatus of claim 1, further comprising reversing a pin arrangement of a positive and a negative signal of a differential signal pair on a pinout for one or more differential signal pairs on the pinout. ### Claim 13 (depends on 1) The apparatus of claim 1, further comprising reversing a pin arrangement of a positive and a negative signal of a differential signal pair on a first pinout for one or more differential signal pairs on the connector relative to a corresponding near pin arrangement of a positive and a negative signal of a differential signal pair on a second pinout. ### Claim 14 (depends on 1) The apparatus of claim 1, wherein the crosstalk is cancelled or reduced to an acceptable level. ### Claim 15 (depends on 1) The apparatus of claim 1, wherein the pinout is a section of a pinout. ### Claim 16 (depends on 1) The apparatus of claim 1, wherein the pinout at least one of a connector, a socket, a section of a connector, a section of a socket, a connector and a socket, or a section of a connector and a socket. ### Claim 17 An apparatus comprising: a first pinout having a pin arrangement of a plurality of differential signal pairs; and a second pinout having a pin arrangement of a plurality of differential signal pairs; wherein the first pinout and the second pinout are near each other and the pin arrangement of the first pinout and the pin arrangement of the second pinout are arranged to reduce or cancel crosstalk. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein a pin arrangement of a positive and a negative signal of a differential signal pair on the first pinout for one or more differential signal pairs are reversed relative to a corresponding near pin arrangement of a positive and a negative signal of a differential signal pair on the second pinout. ### Claim 19 (depends on 17) The apparatus of claim 17, wherein the differential signal pairs comprise high speed serial links. ### Claim 20 (depends on 17) The apparatus of claim 17, wherein the crosstalk is cancelled or reduced to an acceptable level. ### Claim 21 (depends on 17) The apparatus of claim 17, wherein the pinout is a section of a pinout. ### Claim 22 (depends on 17) The apparatus of claim 17, wherein the pinout is at least one of a connector, a socket, a section of a connector, a section of a socket, a connector and a socket, or a section of a connector and a socket.