# US 2013/0278347 A1 · Compensation for digitally controlled oscillator apparatus and method

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0278347 A1
- Document ID: US20130278347A1
- Status: Published application
- Kind: A1
- Application number: 13/997,589
- Filed: 2011-11-09
- Published: 2013-10-24
- Earliest claimed: 2011-11-09
- Assignees: Intel Corporation
- Inventors: Shenggao Li
- Web page: https://patentgrep.com/patent/US20130278347A1

## CPC

- H03L 7/0991: {the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814)}
- H03B 1/00: Details
- H03L 1/00: Stabilisation of generator output against variations of physical values, e.g. power supply
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H03L 7/104: {using an additional signal from outside the loop for setting or controlling a parameter in the loop (H03L7/107, H03L7/12 take precedence)}
- H03L 7/16: Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L 2207/06: Phase locked loops with a controlled oscillator having at least two frequency control terminals
- H03L 2207/50: All digital phase-locked loop
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H)

## Abstract

Automatic digital sensing and compensation of frequency drift caused by temperature, aging, and/or other effects may be provided by including a compensation capacitor array and a sensing logic. The sensing logic may be configured to detect a drift in a first control signal and to provide the compensation capacitor array with a second control signal. The second control signal is configured to cause an adjustment of capacitance in the compensation capacitor array based on the detected drift in the first control signal.

## Claims

### Claim 1

An apparatus, comprising:
a first capacitor array; and
a sensing logic coupled to the first capacitor array and configured to detect a drift in a first control signal and to provide the first capacitor array with a second control signal, wherein the second control signal is configured to cause an adjustment of capacitance in the first capacitor array based on the detected drift in the first control signal.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first capacitor array is configured to compensate for temperature or aging in a phase-locked loop.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising:
a second capacitor array to receive the first control signal and to provide fine frequency tuning in a phase-locked loop.

### Claim 4 (depends on 1)

The apparatus of claim 1, further comprising:
a third capacitor array coupled to receive a third control signal to enable or disable capacitors in the third capacitor array to provide coarse frequency tuning.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the second control signal is configured to cause the adjustment of capacitance in the first capacitor array by enabling or disabling capacitors in the first capacitor array.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the sensing logic is configured to detect the drift in the first control signal based at least in part on a deviation from a threshold.

### Claim 7 (depends on 1)

The apparatus of claim 1, further comprising:
a digital loop filter logic coupled to provide a phase difference to the sensing logic.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the sensing logic is included in a digital loop filter.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the first capacitor array includes a plurality of fine-tuning capacitor arrays identical to a second capacitor array coupled to the sensing logic.

### Claim 10

A method, comprising:
detecting by a detection circuit, a drift in a first control word; and
based at least in part on the detected drift, adjusting by the detection circuit, a second control word to be provided to a first capacitor array to cause an adjustment in capacitance based on the detected drift in the first control word.

### Claim 11 (depends on 10)

The method of claim 10, wherein the adjustment in capacitance is configured to re-center a frequency of a digitally controlled oscillator that includes the first capacitor array.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
providing the first control word to a second capacitor array to cause fine frequency tuning in the second capacitor array.

### Claim 13 (depends on 10)

The method of claim 10, further comprising:
receiving, by the detection circuit, a digital output signal from a digital loop filter logic.

### Claim 14 (depends on 10)

The method of claim 10, wherein the detecting and adjusting occur in an all-digital phase locked loop.

### Claim 15 (depends on 10)

The method of claim 10, wherein the detecting the drift in the first control word includes detecting a frequency deviation from a center of a fine-tuning curve.

### Claim 16 (depends on 10)

The method of claim 10, wherein the detecting the drift in the first control word includes comparing the first control word to a threshold control value.

### Claim 17

A system, comprising:
a processor;
a communication interface coupled to the processor, the communication interface including:
a first capacitor array;
a second capacitor array; and
a sensing logic coupled to the first capacitor array and the second capacitor array; and
a memory including a non-transitory computer readable medium having instructions executable by the processor to cause the communication interface to:
detect by the sensing logic a drift in a first control word; and
based at least in part on the detected drift, adjust, a second control word to be provided to the first capacitor array to cause an adjustment in capacitance based on the detected drift in the first control word.

### Claim 18 (depends on 17)

The system of claim 17, wherein the first capacitor array, the second capacitor array, and the sensing logic are included in a digitally controlled oscillator.

### Claim 19 (depends on 18)

The system of claim 18, further comprising:
a third capacitor array in the digitally controlled oscillator to provide coarse frequency tuning.

### Claim 20 (depends on 19)

The system of claim 19, wherein the third capacitor array is configured to provide the coarse frequency tuning by cancelling process-voltage-temperature variation.

### Claim 21 (depends on 17)

The system of claim 17, further comprising:
a digital loop filter logic coupled to provide a signal including a phase difference to the sensing logic.

### Claim 22 (depends on 17)

The system of claim 17, wherein the first capacitor array, the second capacitor array, and the sensing logic are included in an all-digital phase-locked loop.