High-Frequency Switching Circuit

A high-frequency switching circuit, comprising:

• a first high-frequency switching transistor;
• a second high-frequency switching transistor;
• a third high-frequency switching transistor;
• a fourth high-frequency switching transistor;
• and
• a switch state control circuit;
• wherein a high-frequency series signal path extends via channel-paths of the first and the second high-frequency switching transistors;
• wherein a high-frequency shunt signal path extends via channel-paths of the third and the fourth high-frequency switching transistors;
• wherein a first channel terminal of the first high-frequency switching transistor is coupled to a first high-frequency signal connector of the high-frequency switching circuit;
• wherein a second channel terminal of the first high-frequency switching transistor is coupled to a potential node via a first channel resistor;
• wherein a gate of the first high-frequency switching transistor is coupled to a first switch state signal line of the high-frequency switching circuit via a first gate resistor;
• wherein a first channel terminal of the second high-frequency switching transistor is coupled to the second channel terminal of the first high-frequency switching transistor;
• wherein a second channel terminal of the second high-frequency switching transistor is coupled to the potential node;
• wherein a gate of the second high-frequency switching transistor is coupled to the first switch state signal line via a second gate resistor;
• wherein a first channel terminal of the third high-frequency switching transistor is coupled to the potential node;
• wherein a second channel terminal of the third high-frequency switching transistor is coupled to the potential node via a second channel resistor;
• wherein a gate of the third high-frequency switching transistor is coupled to a second switch state signal line via a third gate resistor;
• wherein a first channel terminal of the fourth high-frequency switching transistor is coupled to the second channel terminal of the third high-frequency switching transistor;
• wherein a second channel terminal of the fourth high-frequency switching transistor is coupled to a reference potential node;
• wherein a gate of the fourth high-frequency switching terminal is coupled to the second switch state signal line via a fourth gate resistor;
• wherein the switch state control circuit is configured to selectively apply at least two different potentials to the first and the second switch state signal line, to selectively place the channel-paths of the third and the fourth high-frequency switching transistors in a high impedance state when the channel-paths of the first and second high-frequency switching transistors are in a low impedance state, or to place the channel-paths of the third and fourth high-frequency switching transistors in a low impedance state when the channel-paths of the first and the second high-frequency switching transistors are in a high impedance state;
• wherein the high-frequency switching circuit is configured to establish a DC-path between the potential node and the reference potential node when the channel-paths of the first and second high-frequency switching transistors are in the high impedance state, by placing at least the channel-path of the fourth high-frequency switching transistor in a low impedance state;
• and
• wherein a potential of the reference potential node is chosen, such that channel regions of the first and the second high-frequency switching transistors are depleted, when the DC-path between the potential node and the reference potential node is established.

A method for operating a high-frequency switching circuit having a first high-frequency switching transistor, a second high-frequency switching transistor, and a control circuit, wherein a second channel terminal of the first high-frequency switching transistor is coupled to a potential node via a first channel resistor, a first channel terminal of the second high-frequency switching transistor is coupled to the second channel terminal of the first high-frequency switching transistor, and a second channel terminal of the second high-frequency switching transistor is coupled to the potential node, wherein the method comprises:

• applying a first potential to a substrate of the first high-frequency switching transistor;
• applying a second potential to a substrate of the second high-frequency switching transistor;
• determining whether the first and second high-frequency switching transistors are in a high impedance state or a low impedance state;
• and
• altering the potential node based on the determining whether the first and second high-frequency switching transistors are in a high impedance state or a low impedance state.