Synchronization of multiple signal converters
AssigneeAnalog Devices, Inc.
InventorsLawrence GETZIN, Petre MINCIUNESCU
Life of this patent
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Abstract
The present invention may provide a system including a controller and a plurality of integrated circuits. The controller may control synchronization operations of the system, the controller may include a master timing counter and a controller data interface. Each integrated circuit may include a timing counter and an IC data interface. Further, each integrated circuit may synchronize its respective timing counter based on synchronization command received from the controller via the data interfaces. Hence, the system may provide synchronization between the controller and the integrated circuits without an extraneous designated pin(s) for a designated common time-based signal.
Claims22
A system, comprising:
- a controller to control synchronization operations of the system, the controller comprises a master timing counter and a controller data interface;
- and
- a plurality of integrated circuits, each integrated circuit integrated circuit comprises a timing counter and an IC data interface, and each integrated circuit to synchronize its respective timing counter based on synchronization command received from the controller via the data interfaces.
A synchronization method between a master controller and a plurality of slave integrated circuits, comprising:
- transmitting a latch command to the integrated circuits, the latch command being associated with a timing counter value;
- receiving timing counter values from the integrated circuits;
- comparing the timing counter values to a stored reference value to determine whether each integrated circuit is in sync or out of sync;
- and
- for each integrated circuit determined to be out of sync, calculating a correction offset value unique to that integrated circuit and transmitting the correction offset value to the out of sync integrated circuit.
A synchronization method for a slave integrated circuit, comprising:
- responsive to a latch command from a master controller, storing a current timing counter value from a timing counter to a register;
- transmitting the timing counter value to the master controller;
- receiving a correction offset value from the master controller;
- in a next operation cycle, operating the timing counter based on the correction offset value;
- and
- after operating the timing counter based on the correction offset value to synchronize with the master controller, return to operating the timing counter based on a common value.
An integrated circuit, comprising:
- a signal converting section to operate on a first supply voltage;
- a control section to operate on a second supply voltage;
- and
- an isolation barrier to separate the signal converting section and the control section;
- wherein the control section comprises
- a data interface to communicate bi-directionally with a controller, and
- a time base counter,
- wherein the time base counter to operate based on a common value unless a correction offset value is received from the controller, then the time base counter to operate based on the correction offset value for a next cycle, and then return to operate based on the common value.
A controller, comprising:
- a register to store a master time value;
- a data interface to communicate with multiple slave units;
- and
- a processor to
- based on received slave unit counter values, determining if each slave unit is in sync or out of sync by comparing the counter values to the master time value;
- and
- for each out of sync slave unit, calculating an offset correction value based on that slave unit's counter value and transmitting the offset correction value to that slave unit.
Dependencies are inferred from the claim text.