# US 2013/0278309 A1 · Semiconductor wafer and method for auto-calibrating integrated circuit chips using pll at wafer level

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- Number: US 2013/0278309 A1
- Document ID: US20130278309A1
- Status: Published application
- Kind: A1
- Application number: 13/605,554
- Filed: 2012-09-06
- Published: 2013-10-24
- Earliest claimed: 2012-04-23
- Assignees: Electronics and Telecommunications Research Institute
- Inventors: Hyunseok KIM; Su Na Choi; Heyung Sub Lee; Cheol Sig Pyo
- Web page: https://patentgrep.com/patent/US20130278309A1

## CPC

- G06K 19/0726: {the arrangement including a circuit for tuning the resonance frequency of an antenna on the record carrier}
- G06K 19/0722: {comprising an arrangement for testing the record carrier}
- G06K: GRAPHICAL DATA READING (image or video recognition or understanding G06V); PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS

## Abstract

In integrated circuit chips that are used for RFID, a method of calibrating an operation frequency that is generated in an operation frequency generator and a semiconductor wafer including a calibration circuit are provided. The method of calibrating an operation frequency of integrated circuit chips includes: supplying DC power to the integrated circuit chips; selecting an integrated circuit chip to perform calibration of an operation frequency; receiving an operation frequency that is generated in the selected integrated circuit chip; calculating a difference between a phase of the operation frequency and a phase of a calibration target frequency; generating a frequency calibration value of the operation frequency using the phase difference; transmitting a control signal including the frequency calibration value to the integrated circuit chip; and releasing a selection of the integrated circuit chip in which calibration of the operation frequency is complete.

## Claims

### Claim 1

A method of auto-calibrating integrated circuit chips at a wafer level by calibrating an operation frequency of the integrated circuit chips, the method comprising:
supplying DC power to the integrated circuit chips;
selecting an integrated circuit chip to perform calibration of an operation frequency;
receiving an operation frequency that is generated in the selected to integrated circuit chip;
calculating a difference between a phase of the operation frequency and a phase of a calibration target frequency;
generating a frequency calibration value of the operation frequency using the phase difference;
transmitting a control signal comprising the frequency calibration value to the integrated circuit chip; and
releasing a selection of the integrated circuit chip in which calibration of the operation frequency is complete.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
after the transmitting of a control signal,
calibrating the operation frequency according to the frequency calibration value that is included in the control signal; and
storing the frequency calibration value at the integrated circuit chip according to the control signal.

### Claim 3

A semiconductor wafer for auto-calibrating an operation frequency of integrated circuit chips, the semiconductor wafer comprising:
an integrated circuit chip area;
a probe area in which a calibration controller of an operation frequency is connected to the outside of the semiconductor wafer, wherein the calibration controller includes a phase-locked loop that calculates a phase difference by comparing a phase of a calibration target frequency and a phase of the operation frequency, and generates an operation frequency calibration value using the phase difference;
a signal transmitting area that is connected to the probe area to transmit a signal of the integrated circuit chips to the calibration controller; and
a buffer that relays a signal that is exchanged between the integrated circuit chips and the signal transmitting area.

### Claim 4 (depends on 3)

The semiconductor wafer of claim 3, wherein the signal transmitting area comprises:
a chip selection bus that transmits a selection signal of the calibration controller for an integrated circuit chip to perform calibration of the operation frequency and a selection release signal for the integrated circuit chip in which calibration of the operation frequency is complete;
an external power line that transmits DC power that is supplied to the integrated circuit chip;
a frequency measurement line that transmits an operation frequency that is generated in the integrated circuit chip; and
a calibration bus that transmits a control signal for calibrating the operation frequency,
wherein the chip selection bus, the external power line, the frequency measurement line, and the calibration bus are connected to the probe area.

### Claim 5 (depends on 4)

The semiconductor wafer of claim 4, wherein the buffer is positioned at an end portion of the chip selection bus and operates according to a selection signal and a selection release signal of the calibration controller, and
when the buffer operates, a connection between the integrated circuit chip, the external power line, the frequency measurement line, and the calibration bus is activated.

### Claim 6

A calibration controller for auto-calibrating an operation frequency of integrated circuit chips, the calibration controller generating an operation frequency calibration value using a phase difference; and
comprising a phase-locked loop that calculates the phase difference by comparing a phase of a calibration target frequency and a phase of the operation frequency.