# US 2013/0278307 A1 · Intelligent power supervisor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0278307 A1 - Document ID: US20130278307A1 - Status: Published application - Kind: A1 - Application number: 13/924,864 - Filed: 2013-06-24 - Published: 2013-10-24 - Earliest claimed: 2011-07-13 - Assignees: Luciano Processing L.L.C. - Applicants: Luciano Processing L.L.C. - Inventors: David G. Wright - Web page: https://patentgrep.com/patent/US20130278307A1 ## CPC - G05F 1/10: Regulating voltage or current (G05F1/02 takes precedence) - G05F 1/46: wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) - G06F 1/24: Resetting means - G06F 13/24: using interrupt (G06F13/32 takes precedence) - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H03L 5/02: of power - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract An intelligent power-on reset circuit in accordance with one embodiment of the invention can include a programmable voltage divider. The intelligent power-on reset circuit can also include a comparator that is coupled to the programmable voltage divider and that is coupled to receive a reference voltage. Furthermore, the intelligent power-on reset circuit can include a processing element that is coupled to the programmable voltage divider. The processing element can be coupled to receive programming for controlling a characteristic of the intelligent power-on reset circuit. The processing element can be for dynamically changing the programming during operation of the intelligent power-on reset circuit. ## Claims ### Claim at position 1 -20. (canceled) ### Claim 21 A system that includes circuitry, comprising: a power supervisor coupled to a power supply voltage, wherein the power supervisor includes: a memory configured to store instructions for asserting a reset output signal to reset the circuitry in response to a reset comparison between a reference voltage and a programmable threshold voltage; a programmable voltage divider configured to provide the programmable threshold voltage as a voltage divided output in response to instructions from the memory; and a programmable reset time module configured to control a time characteristic of the reset output signal. ### Claim 22 (depends on 21) The system of claim 21, wherein the programmable reset time module comprises a programmable reset delay module configured to programmably set a reset delay period to delay resetting of the circuitry to a selected state. ### Claim 23 (depends on 22) The system of claim 22, wherein the selected state to which the circuitry is reset is a power-on state. ### Claim 24 (depends on 21) The system of claim 21, wherein the programmable reset time module comprises a glitch detection module configured to override reset comparisons between the reference voltage and the programmable threshold voltage that are less than a programmed duration. ### Claim 25 (depends on 22) The system of claim 22, wherein the programmable reset time module further comprises a glitch detection module configured to override reset comparisons between the reference voltage and the programmable threshold voltage that are less than a programmed duration. ### Claim 26 (depends on 21) The system of claim 21, wherein the memory is further configured to store instructions for asserting an interrupt signal to interrupt an operation of the circuitry in response to an interrupt comparison between the reference voltage and the programmable threshold voltage. ### Claim 27 (depends on 21) The system of claim 21, further comprising a comparator with inputs configured to receive the reference voltage and the programmable threshold voltage and to provide the reset comparison therebetween. ### Claim 28 (depends on 26) The system of claim 26, further comprising a comparator with inputs configured to receive the reference voltage and a second programmable threshold voltage and to provide the interrupt comparison therebetween. ### Claim 29 (depends on 27) The system of claim 27, wherein the memory is further configured to store instructions for asserting an interrupt signal to interrupt an operation of the circuitry in response to an interrupt comparison between the reference voltage and the programmable threshold voltage, and wherein the system further comprises another comparator with inputs configured to receive the reference voltage and a second programmable threshold voltage and to provide the interrupt comparison therebetween. ### Claim 30 (depends on 21) The system of claim 21, further comprising a processing element configured by instructions stored in the memory to assert the reset output signal in response to the reset comparison. ### Claim 31 A system that includes circuitry, comprising: a power supervisor coupled to a power supply voltage, wherein the power supervisor includes: a comparator; a memory configured to store instructions for asserting a reset output signal to reset the circuitry in response to a reset comparison between a reference voltage and a programmable threshold voltage made by the comparator; a programmable voltage divider configured to provide the programmable threshold voltage as a voltage divided output in response to instructions from the memory; and a programmable reset time module configured to control a time characteristic of the reset output signal. ### Claim 32 (depends on 31) The system of claim 31, wherein the programmable reset time module comprises a programmable reset delay module configured to programmably set a reset delay period to delay resetting of the circuitry to a selected state. ### Claim 33 (depends on 32) The system of claim 32, wherein the selected state to which the circuitry is reset is a power-on state. ### Claim 34 (depends on 31) The system of claim 31, wherein the programmable reset time module comprises a glitch detection module configured to override reset comparisons between the reference voltage and the programmable threshold voltage that are less than a programmed duration. ### Claim 35 (depends on 32) The system of claim 32, wherein the programmable reset time module further comprises a glitch detection module configured to override reset comparisons between the reference voltage and the programmable threshold voltage that are less than a programmed duration. ### Claim 36 (depends on 31) The system of claim 31, wherein the memory is further configured to store instructions for asserting an interrupt signal to interrupt an operation of the circuitry in response to an interrupt comparison between the reference voltage and the programmable threshold voltage. ### Claim 37 (depends on 36) The system of claim 36, further comprising another comparator with inputs configured to receive the reference voltage and a second programmable threshold voltage and to provide the interrupt comparison therebetween. ### Claim 38 (depends on 31) The system of claim 31, further comprising a processing element configured by instructions stored in the memory to assert the reset output signal in response to the reset comparison.