Auto frequency calibration for a phase locked loop and method of use

A method of synchronizing two signals, the method comprising:

• detecting a phase difference between two signals using a phase difference detector;
• setting an initial value of fine tuning signal and generating a coarse tuning signal based on the detected phase difference using a code generator;
• changing the output frequency according to the value of coarse tuning signal;
• generating a fine tuning signal based on the detected phase difference through a digital loop filter after all the bits of coarse tuning signal are decided;
• and
• fine tuning the output frequency until the two signals are synchronized.

A semiconductor device, wherein the semiconductor device is configured to receive a signal and the semiconductor device comprises:

• a phase locked loop (PLL) comprising:
• a phase difference detector configured to receive a reference frequency from the external device and a divider frequency, the phase different detector configured to output a phase difference signal;
• a code generator configured to receive the reference frequency and the phase difference signal, the code generator configured to output a coarse tuning signal and a reset signal;
• a digital loop filter configured to receive the phase difference signal, the digital loop filter configured to output a fine tuning signal;
• a voltage control oscillator configured to receive the coarse tuning signal and the fine tuning signal, the voltage control oscillator configured to output an output frequency;
• a divider configured to receive the reset signal, a divider number control signal and a feedback from the output frequency, the divider configured to output the divider frequency;
• and
• a delta-sigma modulator configured to receive a divisor ratio and the reset signal, the delta-sigma modulator configured to output parts of the fractional number to code generator for determining the sampling period number N.