# US 2013/0278294 A1 · Interpolation circuit, reception circuit and method of generating interpolated data > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0278294 A1 - Document ID: US20130278294A1 - Status: Published application - Kind: A1 - Application number: 13/827,726 - Filed: 2013-03-14 - Published: 2013-10-24 - Earliest claimed: 2012-04-23 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Takayuki SHIBASAKI - Web page: https://patentgrep.com/patent/US20130278294A1 ## CPC - H03K 5/00: Manipulating of pulses not covered by one of the other main groups of this subclass (circuits with regenerative action H03K3/00, H03K4/00; by the use of non-linear magnetic or dielectric devices H03K3/45) - H03M 1/203: {using an analogue interpolation circuit} - H04B 1/00: Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04B: TRANSMISSION ## Abstract An interpolation circuit includes: a generation circuit configured to generate interpolated data based on a plurality of pieces of input data in time sequence; a first analog digital converter configured to convert first interpolated data at a data point of the interpolated data into first digital data; and a second analog digital converter configured to convert second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter. ## Claims ### Claim 1 An interpolation circuit comprising: a generation circuit configured to generate interpolated data based on a plurality of pieces of input data in time sequence; a first analog digital converter configured to convert first interpolated data at a data point of the interpolated data into first digital data; and a second analog digital converter configured to convert second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter. ### Claim 2 (depends on 1) The interpolation circuit according to claim 1, further comprising: an equalization circuit configured to equalize interpolated data at the data point. ### Claim 3 (depends on 2) The interpolation circuit according to claim 2, wherein the equalization circuit includes a decision feedback equalizer. ### Claim 4 (depends on 1) The interpolation circuit according to claim 1, wherein the generation circuit, based on a selection of pieces of input data adjacent in time sequence from among the plurality of pieces of input data, outputs the first interpolated data to the first analog digital converter and outputs the second interpolated data to the second analog digital converter. ### Claim 5 (depends on 4) The interpolation circuit according to claim 4, wherein the selection is performed based on a phase difference between the input data and the interpolated data. ### Claim 6 (depends on 1) The interpolation circuit according to claim 1, further comprising: a selection circuit configured to select at least one of the first interpolated data and the second interpolated data. ### Claim 7 (depends on 6) The interpolation circuit according to claim 6, wherein the selection circuit performs a selection based on a phase difference between the input data and the interpolated data. ### Claim 8 (depends on 1) The interpolation circuit according to claim 1, wherein the number of quantization bits of the second analog digital converter corresponds to one bit. ### Claim 9 A reception circuit comprising: an interpolation circuit configured to output interpolated data based on input data input in time sequence; and a calculation circuit configured to detect a phase difference between the input data and the interpolated data, wherein the interpolation circuit includes a generation circuit configured to generate the interpolated data, a first analog digital converter configured to convert the interpolated data at a data point into digital data, and a second analog digital converter configured to convert the interpolated data at a change point into digital data, a number of quantization bits of the second analog digital converter is smaller than a number of quantization bits of the first analog digital converter. ### Claim 10 (depends on 9) The reception circuit according to claim 9, wherein the calculation circuit calculates a phase difference between the input data and the interpolated data, using interpolated data at the change point. ### Claim 11 (depends on 9) The reception circuit according to claim 9, wherein the interpolation circuit further comprises: an equalization circuit configured to equalize interpolated data at the data point. ### Claim 12 (depends on 11) The reception circuit according to claim 11, wherein the equalization circuit includes a decision feedback equalizer. ### Claim 13 (depends on 9) The reception circuit according to claim 9, wherein the generation circuit, based on a selection of pieces of input data adjacent in time sequence from among the plurality of pieces of input data, outputs the first interpolated data to the first analog digital converter and outputs the second interpolated data to the second analog digital converter. ### Claim 14 (depends on 13) The reception circuit according to claim 13, wherein the selection is performed based on a phase difference between the input data and the interpolated data. ### Claim 15 (depends on 9) The reception circuit according to claim 9, further comprising: a selection circuit configured to select at least one of the first interpolated data and the second interpolated data. ### Claim 16 (depends on 15) The reception circuit according to claim 15, wherein the selection circuit performs a selection based on a phase difference between the input data and the interpolated data. ### Claim 17 (depends on 9) The reception circuit according to claim 9, wherein the number of quantization bits of the second analog digital converter corresponds to one bit. ### Claim 18 A method of generating interpolated data, the method comprising: generating interpolated data based on a plurality of pieces of input data in time sequence; converting first interpolated data at a data point of the interpolated data into first digital data; and converting second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter. ### Claim 19 (depends on 18) The method according to claim 18, further comprising: calculating a phase difference between the input data and the interpolated data, using interpolated data at a change point. ### Claim 20 (depends on 18) The method according to claim 18, further comprising: equalizing interpolated data at the data point.