# US 2013/0278291 A1 · Multifunction word recognizer element > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0278291 A1 - Document ID: US20130278291A1 - Status: Published application - Kind: A1 - Application number: 13/922,125 - Filed: 2013-06-19 - Published: 2013-10-24 - Earliest claimed: 2009-01-16 - Assignees: Tektronix, Inc. - Applicants: Tektronix, Inc. - Inventors: John F. STOOPS; Daniel G. KNIERIM - Web page: https://patentgrep.com/patent/US20130278291A1 ## CPC - H03K 5/2481: {with at least one differential stage} - G01R 31/3177: Testing of logic operation, e.g. by logic analysers - G01R 13/0254: {for triggering, synchronisation} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A circuit includes a load; a first differential pair coupled to the load and responsive to input data; a second differential pair coupled to the load and responsive to the input data; a third differential pair coupled to the first differential pair and the second differential pair and responsive to a first control signal and a second control signal; a bias circuit configured to pull a node coupled to both the first differential pair and the second differential pair to a predetermined state; and a current source coupled to the third differential pair and the bias circuit. ## Claims ### Claim 1 A circuit, comprising: a load; a first differential pair coupled to the load and responsive to input data; a second differential pair coupled to the load and responsive to the input data; a third differential pair coupled to the first differential pair and the second differential pair and responsive to a first control signal and a second control signal; a bias circuit configured to pull a node coupled to both the first differential pair and the second differential pair to a predetermined state; and a current source coupled to the third differential pair and the bias circuit. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the current source includes a resistor coupled between a power supply node and a node coupled to both the third differential pair and the bias circuit. ### Claim 3 (depends on 1) The circuit of claim 1, wherein the bias circuit comprises: a voltage source; and a transistor coupled between the current source and the node coupled to both the first differential pair and the second differential pair; wherein the transistor is responsive to a voltage of the voltage source. ### Claim 4 (depends on 3) The circuit of claim 3, wherein the bias circuit further comprises a resistor network coupled to a power supply and the transistor. ### Claim 5 (depends on 3) The circuit of claim 3, wherein the voltage source is configured to generate the voltage at a level substantially between a first logic level of the first control signal and a second logic level of the first control signal. ### Claim 6 (depends on 1) The circuit of claim 1, further comprising a variable capacitor coupled to the load. ### Claim 7 (depends on 6) The circuit of claim 6, wherein: the load includes a first node and a second node; the variable capacitor is coupled between the first node and the second node; and the first differential pair and the second differential pair are cross-coupled to the first node and second node. ### Claim 8 (depends on 1) The circuit of claim 1, further comprising: a cascode transistor stage coupled between the load, and the first differential pair and the second differential pair; and a variable capacitance coupled to the load and the cascode transistor stage. ### Claim 9 (depends on 1) The circuit of claim 1, wherein the first differential pair and the second differential pair are both responsive to a data signal and a complementary data signal of the input data. ### Claim 10 (depends on 1) The circuit of claim 1, further comprising control circuitry configured to generate the first control signal and the second control signal in response to a do-not-care signal and a desired data signal. ### Claim 11 (depends on 10) The circuit of claim 10, wherein the control circuitry is configured to generate the first control signal by performing a logical AND operation on an inverse of the do-not-care signal and the desired data signal. ### Claim 12 (depends on 11) The circuit of claim 11, wherein the control circuitry is configured to generate the second control signal by performing a logical AND operation on the inverse of the do-not-care signal and an inverse of the desired data signal. ### Claim 13 A circuit, comprising: a first transistor coupled between a first node and a second node and responsive to a data signal; a second transistor coupled between a third node and the second node and responsive to an inverted data signal; a third transistor coupled between the third node and a fourth node and responsive to the data signal; a fourth transistor coupled between the first node and the fourth node and responsive to the inverted data signal; a fifth transistor coupled between the second node and a fifth node and responsive to a first control signal; a sixth transistor coupled between the fourth node and the fifth node and responsive to a second control signal; and a seventh transistor coupled between the first node, the fifth node, and a voltage source. ### Claim 14 (depends on 13) The circuit of claim 13, wherein transition frequencies of the fifth, sixth, and seventh transistors are less than half of transition frequencies of the first through fourth transistors. ### Claim 15 (depends on 13) The circuit of claim 13, further comprising a resistor coupled between the seventh transistor and the first node. ### Claim 16 (depends on 13) The circuit of claim 13, further comprising a resistor coupled between the fifth node and a power supply terminal. ### Claim 17 (depends on 13) The circuit of claim 13, further comprising a variable capacitor coupled between the first node and the third node.