# US 2013/0278290 A1 · Programmable high-speed i/o interface

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- Number: US 2013/0278290 A1
- Document ID: US20130278290A1
- Status: Published application
- Kind: A1
- Application number: 13/925,482
- Filed: 2013-06-24
- Published: 2013-10-24
- Earliest claimed: 2001-08-29
- Assignees: Altera Corporation
- Applicants: Altera Corporation
- Inventors: Bonnie I. Wang; Chiakang Sung; Joseph Huang; Khai Q. Nguyen; Philip Y. Pan
- Web page: https://patentgrep.com/patent/US20130278290A1

## CPC

- H03K 19/17744: {for input/output signals}
- H03K 19/017509: {Interface arrangements}
- H03K 19/017581: {programmable}
- H03K 19/1774: {for global signals, e.g. clock, reset}
- H03K 19/17788: for input/output [I/O] voltages
- H03K 19/0175: Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

## Claims

### Claim 1

An integrated circuit comprising:
a differential input buffer having a first input coupled to a first pad and a second input coupled to a second pad;
a first single-ended input buffer having an input coupled to the first pad;
a second single-ended input buffer having an input coupled to the second pad;
a first single-ended output buffer having an output coupled to the first pad;
a second single-ended output buffer having an output coupled to the second pad;
a serial-to-parallel converter having an input coupled to an output of the differential input buffer; and
a parallel-to-serial converter having an output coupled to an input of the first single-ended output buffer.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 further comprising:
a first output double data-rate register having an output coupled to the input of the first single-ended output buffer;
a second output double data-rate register having an output coupled to the input of the second single-ended output buffer;
a first tristate double data-rate register having an output coupled to an enable input of the first single-ended output buffer; and
a second tristate double data-rate register having an output coupled to an enable input of the second single-ended output buffer.

### Claim 3 (depends on 2)

The integrated circuit of claim 2 further comprising:
an adjustable delay line coupled between the output of the differential input buffer and the input of the serial-to-parallel converter.

### Claim 4 (depends on 2)

The integrated circuit of claim 2 further comprising:
an adjustable delay line to delay an input signal received at the first pad.

### Claim 5 (depends on 4)

The integrated circuit of claim 4 wherein the adjustable delay line comprises a plurality of taps.

### Claim 6 (depends on 4)

The integrated circuit of claim 4 further comprising:
a plurality of programmable logic elements configurable to implement user-defined logic functions.

### Claim 7 (depends on 4)

The integrated circuit of claim 4 wherein the differential input buffer is configurable to receive low-voltage differential signaling (LVDS) compliant signals.

### Claim 8 (depends on 4)

The integrated circuit of claim 4 further comprising:
a multiplexer having a first input coupled to the output of the differential input buffer, a second input coupled to the output of the first single-ended input buffer, and an output coupled to an input of an input double data-rate register.

### Claim 9 (depends on 4)

The integrated circuit of claim 4 wherein the first output double data-rate register comprises:
a first register;
a second register; and
a multiplexer having a first input coupled to an output of the first register, a second input coupled to an output of the second register, and an output coupled to an input of the first single-ended input buffer.

### Claim 10 (depends on 4)

The integrated circuit of claim 4 wherein the first tristate double data-rate register each comprises:
a first register; and
a second register having an input coupled to an output of the first register and an output coupled to the enable input of the first single-ended output buffer.