# US 2013/0278288 A1 · Ic output signal path with switch, bus holder, and buffer

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- Number: US 2013/0278288 A1
- Document ID: US20130278288A1
- Status: Published application
- Kind: A1
- Application number: 13/855,955
- Filed: 2013-04-03
- Published: 2013-10-24
- Earliest claimed: 1995-04-28
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US20130278288A1

## CPC

- H03K 19/173: using elementary logic circuits as components
- G01R 31/31713: {Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572)}
- G01R 31/31715: {Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer}
- G01R 31/318572: {Input/Output interfaces}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal. The signal path includes a switch (S), a bus holder circuit (121B), and an output buffer (19).

## Claims

### Claim 1

An integrated circuit comprising:
A. functional logic having a functional output lead and a control output lead;
B. a three state output buffer having an input, an output lead, and a control input;
C. a serial in data lead;
D. a first multiplexer having an output, a first input coupled to the functional output lead, and a second input coupled to the serial in data lead;
E. a first memory circuit having an input coupled to the output of the first multiplexer and having an output coupled to the input of the three sate output buffer;
F. a second multiplexer having an output, a first input coupled to the control output lead, and a second input coupled to the output of the first memory circuit;
G. a second memory circuit having an output and an input coupled to the output of the second multiplexer;
H. a serial out data lead coupled to the output of the second memory circuit; and
I. a latching control buffer having an input coupled to the output of the second memory circuit, a control input, and an output coupled to the control input of the three state output buffer.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 in which the latching control buffer includes a switch circuit having a control lead coupled to the control input.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 in which the latching control buffer includes a switch circuit having an input coupled to the control output lead of the functional logic, a control lead coupled to the control input, and a switch output, and including an output buffer circuit coupled between the switch output and the output of the latching control buffer, and including an input buffer coupled between the switch circuit output and the output of the latching control buffer.

### Claim 4 (depends on 1)

The integrated circuit of claim 1 in which the latching control buffer includes a switch circuit having an input coupled to the control output lead of the functional logic, a control lead coupled to the control input, and a switch output, and including an output buffer circuit coupled between the switch output and the output of the latching control buffer, and including an input buffer coupled between the switch circuit output and the output of the latching control buffer, the input buffer being weaker than the output buffer circuit.