# US 2013/0278285 A1 · Minimum-spacing circuit design and layout for pica

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- Number: US 2013/0278285 A1
- Document ID: US20130278285A1
- Status: Published application
- Kind: A1
- Application number: 13/452,092
- Filed: 2012-04-20
- Published: 2013-10-24
- Earliest claimed: 2012-04-20
- Assignees: International Business Machines Corporation
- Inventors: HERSCHEL A. AINSPAN; SEONGWON KIM; FRANCO STELLARI; ALAN J. WEGER
- Web page: https://patentgrep.com/patent/US20130278285A1

## CPC

- H04N 17/002: {for television cameras}
- G01J 1/44: Electric circuits {(for command of an exposure part G03B7/02)}
- G01J 11/00: Measuring the characteristics of individual optical pulses or of optical pulse trains
- G01R 31/26: Testing of individual semiconductor devices (testing of photovoltaic devices H02S50/10; testing or measuring during manufacture or treatment {H10P74/00})
- H03K 19/094: using field-effect transistors
- H03K 19/14: using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled (optical logic elements G02F3/00)
- G01J 2001/4238: {Pulsed light}
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- G01J: MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY (light sources F21, H01J, H01K, H05B; investigating properties of materials by optical means G01N)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology; a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal; and a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal. One of said NOR gates biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered.

## Claims

### Claim 1

A circuit, comprising:
a first semiconductor device and a second semiconductor device which emit light during operation, laid out such that light-emitting regions of the respective semiconductor devices are proximal to one another with a gap between the respective light-emitting regions including a target resolution size; and
a logic circuit configured to accept an input signal and at least one select signal and to bias light-emitting regions of at least one of the respective semiconductor to inhibit an optical emission when said at least one semiconductor device is triggered.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the first and second semiconductor devices are field effect transistors.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein the logic circuit comprises two NOR gates, each accepting respective select signals that alternate logical values.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the at least one select signal comprises two select signals having opposite logical values.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein the semiconductor devices are field effect transistors.

### Claim 6 (depends on 5)

The circuit of claim 5, wherein the logic circuit is configured to bias a drain region of a field effect transistor at a low voltage to inhibit light emission.

### Claim 7

A circuit, comprising:
a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology;
a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal; and
a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal,
wherein one of said NOR gates biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered.

### Claim 8 (depends on 7)

The circuit of claim 7, further comprising:
a third NOR gate accepting the outputs of the first and second NOR gates; and
an inverter accepting the output of the third NOR gate.

### Claim 9 (depends on 8)

The circuit of claim 8, wherein the inverter has an output that conforms to the input signal.

### Claim 10 (depends on 7)

The circuit of claim 7, wherein the first select signal and the second select signal have opposite logical values.

### Claim 11 (depends on 7)

The circuit of claim 7, wherein the first select signal and the second select signal alternate logical values.

### Claim 12 (depends on 11)

The circuit of claim 11, wherein the first select signal and the second select signal alternate logical values at a periodic interval.

### Claim 13 (depends on 7)

The circuit of claim 7, wherein the input signal is a square wave.

### Claim 14 (depends on 7)

The circuit of claim 7, wherein the gap between the respective drain regions has a size of about 70 nm or less.

### Claim 15

A test circuit, comprising:
a plurality of test cells arranged in a line, each test cell comprising:
a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology;
a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal provided by the output of a previous test cell; and
a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal,
wherein one of said NOR gates in each test cell biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered.

### Claim 16 (depends on 15)

The test circuit of claim 15, wherein adjacent test cells are oriented with respect to one another such that the first transistors of the test cells form a first line and the second transistors of the test cells form a second line.

### Claim 17 (depends on 16)

The test circuit of claim 16, wherein the first and second select signals are chosen to provide a line of illumination for optical testing.

### Claim 18 (depends on 15)

The test circuit of claim 15, wherein each test cell further comprises:
a third NOR gate accepting the outputs of the first and second NOR gates; and
an inverter accepting the output of the third NOR gate and producing an output for the test cell.

### Claim 19 (depends on 18)

The test circuit of claim 18, wherein the inverter has an output that conforms to the input signal.

### Claim 20 (depends on 15)

The test circuit of claim 15, wherein the first select signal and the second select signal have opposite logical values.

### Claim 21 (depends on 20)

The test circuit of claim 20, wherein the first select signal and the second select signal alternate logical values at a periodic interval.