# US 2013/0278284 A1 · Semiconductor device and control system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0278284 A1 - Document ID: US20130278284A1 - Status: Published application - Kind: A1 - Application number: 13/858,178 - Filed: 2013-04-08 - Published: 2013-10-24 - Earliest claimed: 2012-04-20 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Kazuki Watanabe; Yosuke Tanno - Web page: https://patentgrep.com/patent/US20130278284A1 ## CPC - H10W 42/405: {using active circuits} - G05F 1/573: with overcurrent detector - G06K 19/0715: {the arrangement including means to regulate power transfer to the integrated circuit} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - G06K: GRAPHICAL DATA READING (image or video recognition or understanding G06V); PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS ## Abstract To enhance the security of a semiconductor device, the semiconductor device has a regulator unit for generating an internal power supply voltage based on a power supply voltage supplied from outside, an internal circuit which operates on the internal power supply voltage, a current detection unit for monitoring a power supply current supplied to the internal circuit, and a control unit for controlling operation of the internal circuit. In the semiconductor device, when the current detection unit detects that the power supply current exceeds a predetermined threshold value, the control unit restricts the operation of the internal circuit. ## Claims ### Claim 1 A semiconductor device comprising: a regulator unit for generating an internal power supply voltage based on a power supply voltage supplied from outside; an internal circuit which operates on the internal power supply voltage; a current detection unit for monitoring a power supply current supplied to the internal circuit; and a control unit for controlling operation of the internal circuit, wherein the internal circuit comprises a data processing unit for executing a program, wherein when the current detection unit detects that the power supply current exceeds a predetermined threshold value, the current detection unit outputs a detection result indicating that, and wherein the control unit restricts the operation of the internal circuit in accordance with the detection result. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the regulator unit comprises: a first MOS transistor for supplying the internal power supply voltage to the internal circuit; and an amplifier unit for adjusting a gate voltage of the first MOS transistor so that the internal power supply voltage is maintained constant, and wherein the current detection unit comprises: a second MOS transistor whose gate voltage is equal to the gate voltage of the first MOS transistor; and a determination unit for determining whether or not the power supply current exceeds the predetermined threshold value, based on a current flowing through the second MOS transistor. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the control unit restricts the operation of the internal circuit by stopping power supply to the internal circuit. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the control unit stops the power supply to the internal circuit by stopping operation of the regulator unit for a predetermined time. ### Claim 5 (depends on 3) The semiconductor device according to claim 3, further comprising a register unit which can be accessed by the data processing unit and in which control information is set, wherein the determination unit changes the predetermined threshold value in accordance with the control information set in the register unit. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the data processing unit changes the control information in accordance with an operation clock frequency of the internal circuit. ### Claim 7 (depends on 5) The semiconductor device according to claim 5, wherein the data processing unit comprises a central processing unit, a storage unit, and a signal processing unit for executing signal processing in accordance with an instruction from the central processing unit, and wherein the central processing unit changes the control information in accordance with presence or absence of execution of signal processing by the signal processing unit. ### Claim 8 (depends on 2) The semiconductor device according to claim 2, wherein the control unit restricts the operation of the internal circuit by stopping supply of an operation clock signal to the internal circuit. ### Claim 9 (depends on 2) The semiconductor device according to claim 2, wherein the control unit restricts the operation of the internal circuit by resetting the internal circuit. ### Claim 10 (depends on 2) The semiconductor device according to claim 2, further comprising a communication terminal for transmitting and receiving a signal, wherein the control unit outputs an error signal indicating occurrence of an abnormality to the communication terminal in accordance with the detection result. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the control unit restricts the operation of the internal circuit by shutting off communication through the communication terminal by the internal circuit. ### Claim 12 (depends on 2) The semiconductor device according to claim 2, wherein the second MOS transistor has s smaller current capability than the first MOS transistor. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the first MOS transistor and the second MOS transistor comprise unit MOS transistors having predetermined gate length and gate width, and wherein the number of unit MOS transistors configuring the second MOS transistor is smaller than the number of unit MOS transistors configuring the first MOS transistor. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the unit MOS transistors configuring the first MOS transistor and the unit MOS transistors configuring the second MOS transistor are formed in the same element formation region so that drains and sources are arranged in the same direction with respect to gates of the respective unit MOS transistors. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the unit MOS transistors configuring the second MOS transistor are arranged dispersedly in the element formation region. ### Claim 16 (depends on 2) The semiconductor device according to claim 2, wherein the determination unit comprises: a current source which is coupled to a drain of the second MOS transistor and generates a reference current corresponding to the predetermined threshold value; and a comparison circuit for comparing magnitudes of the current flowing through the second MOS transistor and the reference current, based on a voltage of a node between the current source and the second MOS transistor, and wherein the comparison circuit outputs the detection result when the current flowing through the second MOS transistor is larger than the reference current. ### Claim 17 (depends on 2) The semiconductor device according to claim 2, wherein the determination unit comprises: a resistive element for converting the current flowing through the second MOS transistor into a voltage; and a comparison circuit for comparing the voltage converted by the resistive element with a reference voltage corresponding to the predetermined threshold value, and wherein the comparison circuit outputs the detection result when the converted voltage is larger. ### Claim 18 (depends on 10) A control system comprising: the semiconductor device according to claim 10; and a control device which controls supply of a power supply voltage to the semiconductor device and transmits and receives a signal to/from the semiconductor device, wherein when the error signal is outputted, the control device stops power supply to the semiconductor device that has outputted the error signal. ### Claim 19 (depends on 18) The control system according to claim 18, comprising a plurality of the semiconductor devices, wherein the semiconductor devices comprise a first semiconductor device which operates as a main terminal and one or a plurality of second semiconductor devices which operate as sub-terminals, and wherein when the error signal is outputted from the first semiconductor device, the control device operates one of the second semiconductor devices as the main terminal. ### Claim 20 (depends on 18) The control system according to claim 18, further comprising sockets in which the semiconductor devices are mounted and electrically couple the semiconductor devices to the control device, wherein the semiconductor devices are detachably coupled to the sockets.